XC3S400AN-4FGG400I Xilinx Inc, XC3S400AN-4FGG400I Datasheet - Page 29
![IC FPGA SPARTAN-3A 400K 400-FBGA](/photos/6/72/67298/pk083-400_sml.jpg)
XC3S400AN-4FGG400I
Manufacturer Part Number
XC3S400AN-4FGG400I
Description
IC FPGA SPARTAN-3A 400K 400-FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S400AN-4FGG400I
Total Ram Bits
368640
Number Of Logic Elements/cells
8064
Number Of Labs/clbs
896
Number Of I /o
311
Number Of Gates
400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
400-BGA
No. Of Logic Blocks
896
No. Of Gates
400000
No. Of Macrocells
8064
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
311
Clock
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S400AN-4FGG400I
Manufacturer:
TOSHIBA
Quantity:
198
Company:
Part Number:
XC3S400AN-4FGG400I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 23: Setup and Hold Times for the IOB Input Path (Cont’d)
Table 24: Sample Window (Source Synchronous)
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
T
Set/Reset Pulse Width
T
Symbol
T
IOICKPD
RPW_IOB
SAMP
Symbol
The numbers in this table are tested using the methodology presented in
Table 10
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from
edge.
Setup and hold
capture window of
an IOB flip-flop.
and
Description
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
Minimum pulse width to SR control
input on IOB
Table
13.
Description
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
• Answer Record
Table
Table
26.
26. When the hold time is negative, it is possible to change the data before the clock’s active
30879
LVCMOS25
Conditions
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
–
(3)
Table 30
Maximum
DELAY_
VALUE
IFD_
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
–
and are based on the operating conditions set forth in
XC3S400AN
XC3S700AN
XC3S1400AN
All
Device
–1.12
–1.70
–2.08
–2.38
–2.23
–2.69
–3.08
–3.35
–1.67
–2.27
–2.59
–2.92
–2.89
–3.22
–3.52
–3.81
–1.60
–2.06
–2.46
–2.86
–2.88
–3.24
–3.55
–3.89
1.33
Min
Speed Grade
-5
–1.12
–1.70
–2.08
–2.38
–2.23
–2.69
–3.08
–3.35
–1.67
–2.27
–2.59
–2.92
–2.89
–3.22
–3.52
–3.81
–1.60
–2.06
–2.46
–2.86
–2.88
–3.24
–3.55
–3.89
1.61
Min
-4
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
29