XC3S400AN-4FGG400I Xilinx Inc, XC3S400AN-4FGG400I Datasheet - Page 51
![IC FPGA SPARTAN-3A 400K 400-FBGA](/photos/6/72/67298/pk083-400_sml.jpg)
XC3S400AN-4FGG400I
Manufacturer Part Number
XC3S400AN-4FGG400I
Description
IC FPGA SPARTAN-3A 400K 400-FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S400AN-4FGG400I
Total Ram Bits
368640
Number Of Logic Elements/cells
8064
Number Of Labs/clbs
896
Number Of I /o
311
Number Of Gates
400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
400-BGA
No. Of Logic Blocks
896
No. Of Gates
400000
No. Of Macrocells
8064
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
311
Clock
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S400AN-4FGG400I
Manufacturer:
TOSHIBA
Quantity:
198
Company:
Part Number:
XC3S400AN-4FGG400I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Block RAM Timing
Table 38: Block RAM Timing
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
T
T
Hold Times
T
T
T
T
Clock Timing
T
T
Clock Frequency
F
RCKO
RCCK_ADDR
RDCK_DIB
RCCK_ENB
RCCK_WEB
RCKC_ADDR
RCKD_DIB
RCKC_ENB
RCKC_WEB
BPWH
BPWL
BRAM
Symbol
The numbers in this table are based on the operating conditions set forth in
When reading from block RAM, the delay from the active
transition at the CLK input to data appearing at the DOUT
output
Setup time for the ADDR inputs before the active transition at
the CLK input of the block RAM
Setup time for data at the DIN inputs before the active
transition at the CLK input of the block RAM
Setup time for the EN input before the active transition at the
CLK input of the block RAM
Setup time for the WE input before the active transition at the
CLK input of the block RAM
Hold time on the ADDR inputs after the active transition at the
CLK input
Hold time on the DIN inputs after the active transition at the
CLK input
Hold time on the EN input after the active transition at the CLK
input
Hold time on the WE input after the active transition at the CLK
input
High pulse width of the CLK signal
Low pulse width of the CLK signal
Block RAM clock frequency
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table
0.32
0.28
0.69
1.12
1.56
1.56
Min
10.
–
0
0
0
0
0
-5
Max
2.06
320
Speed Grade
–
–
–
–
–
–
–
–
–
–
0.36
0.31
0.77
1.26
1.79
1.79
Min
–
0
0
0
0
0
-4
Max
2.49
280
–
–
–
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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