XC3S400AN-4FGG400I Xilinx Inc, XC3S400AN-4FGG400I Datasheet - Page 37
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XC3S400AN-4FGG400I
Manufacturer Part Number
XC3S400AN-4FGG400I
Description
IC FPGA SPARTAN-3A 400K 400-FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S400AN-4FGG400I
Total Ram Bits
368640
Number Of Logic Elements/cells
8064
Number Of Labs/clbs
896
Number Of I /o
311
Number Of Gates
400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
400-BGA
No. Of Logic Blocks
896
No. Of Gates
400000
No. Of Macrocells
8064
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
311
Clock
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S400AN-4FGG400I
Manufacturer:
TOSHIBA
Quantity:
198
Company:
Part Number:
XC3S400AN-4FGG400I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Three-State Output Propagation Times
Table 28: Timing for the IOB Three-State Path
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
Synchronous Output Enable/Disable Times
T
T
Asynchronous Output Enable/Disable Times
T
Set/Reset Times
T
T
IOCKHZ
IOCKON
GTS
IOSRHZ
IOSRON
Symbol
The numbers in this table are tested using the methodology presented in
Table 10
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from
(2)
(2)
and
Time from the active transition at the OTCLK
input of the Three-state Flip-Flop (TFF) to when
the Output pin enters the high-impedance state
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
Time from asserting the Global Three State
(GTS) input on the STARTUP_SPARTAN3A
primitive to when the Output pin enters the
high-impedance state
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
Table
13.
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
LVCMOS25, 12 mA
output drive, Fast slew
rate
LVCMOS25, 12 mA
output drive, Fast slew
rate
LVCMOS25, 12 mA
output drive, Fast slew
rate
Conditions
Table 30
Table
29.
and are based on the operating conditions set forth in
Device
All
All
All
All
All
Speed Grade
Max
0.63
2.80
9.47
1.61
3.57
-5
10.36
Max
0.76
3.06
1.86
3.82
-4
Units
ns
ns
ns
ns
ns
37