XC3S400AN-4FGG400I Xilinx Inc, XC3S400AN-4FGG400I Datasheet - Page 68
![IC FPGA SPARTAN-3A 400K 400-FBGA](/photos/6/72/67298/pk083-400_sml.jpg)
XC3S400AN-4FGG400I
Manufacturer Part Number
XC3S400AN-4FGG400I
Description
IC FPGA SPARTAN-3A 400K 400-FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S400AN-4FGG400I
Total Ram Bits
368640
Number Of Logic Elements/cells
8064
Number Of Labs/clbs
896
Number Of I /o
311
Number Of Gates
400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
400-BGA
No. Of Logic Blocks
896
No. Of Gates
400000
No. Of Macrocells
8064
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
311
Clock
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S400AN-4FGG400I
Manufacturer:
TOSHIBA
Quantity:
198
Company:
Part Number:
XC3S400AN-4FGG400I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 61: Timing for the JTAG
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
T
T
F
Symbol
TCKTDO
TDITCK
TMSTCK
TCKTDI
TCKTMS
CCH
CCL
CCHDNA
CCLDNA
TCK
The numbers in this table are based on the operating conditions set forth in
For details on JTAG, see Chapter 9, “JTAG Configuration Mode and Boundary-Scan” in
Guide.
The time from the falling transition on the TCK pin to data appearing at the TDO pin
The time from the setup of data at the
TDI pin to the rising transition at the
TCK pin
The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
The time from the rising transition at
the TCK pin to the point when data is
last held at the TDI pin
The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
Frequency of the TCK signal
(2)
Test Access Port
All functions except ISC_DNA command
All devices and functions except those shown below
Boundary-Scan commands (INTEST, EXTEST,
SAMPLE) on XC3S700AN and XC3S1400AN FPGAs
All functions except those shown below
Configuration commands (CFG_IN, ISC_PROGRAM)
During ISC_DNA command
All operations on XC3S50AN, XC3S200AN, and
XC3S400AN FPGAs and for BYPASS or HIGHZ
instructions on all FPGAs
All operations on XC3S700AN and XC3S1400AN
FPGAs, except for BYPASS or HIGHZ instructions
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table
10.
UG332
Spartan-3 Generation Configuration User
11.0
Min
1.0
7.0
7.0
2.0
10
10
0
0
5
5
0
All Speed
Grades
10,000
10,000
Max
11.0
33
20
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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