XC5VSX50T-1FF1136I Xilinx Inc, XC5VSX50T-1FF1136I Datasheet - Page 259
![IC FPGA VIRTEX-5 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX50T-1FF1136I
Manufacturer Part Number
XC5VSX50T-1FF1136I
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-1FF1136I
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
HSTL Class III
Figure 6-49
Class III.
X-Ref Target - Figure 6-49
Table 6-19
Table 6-19: HSTL Class III DC Voltage Specifications
Notes:
1. V
2. Per EIA/JESD8-6, “The value of V
V
V
V
V
V
V
V
I
I
OH
OL
CCO
REF
TT
IH
IL
OH
OL
the use conditions specified by the user.”
OL
at V
at V
External Termination
DCI
(2)
and V
HSTL_III_DCI
OL
OH
lists the HSTL Class III DC voltage specifications.
HSTL_III
(mA)
shows a sample circuit illustrating a valid termination technique for HSTL
OH
(mA)
for lower drive currents are sample tested.
(1)
IOB
IOB
(1)
Figure 6-49: HSTL Class III Termination
www.xilinx.com
Z 0
Z 0
REF
R P = Z 0 = 50Ω
is to be selected by the user to provide optimum noise margin in
Specific Guidelines for I/O Supported Standards
V
V
TT
IOB
CCO
= 1.5V
= 1.5V
R
V
V
VRP
CCO
REF
Min
1.40
= Z 0 = 50Ω
–8
24
–
–
–
–
IOB
+ 0.1
V
V
– 0.4
REF
REF
= 0.9V
= 0.9V
V
1.50
0.90
Typ
HSTL_III_DCI
CCO
–
–
–
–
–
–
HSTL_III
+
–
+
–
ug190_6_47_030306
V
REF
Max
1.60
0.4
–
–
–
–
–
–
– 0.1
259
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