XC5VSX50T-1FF1136I Xilinx Inc, XC5VSX50T-1FF1136I Datasheet - Page 372
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XC5VSX50T-1FF1136I
Manufacturer Part Number
XC5VSX50T-1FF1136I
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-1FF1136I
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 8: Advanced SelectIO Logic Resources
Table 8-6: OSERDES Port List and Definitions
372
OQ
SHIFTOUT1
SHIFTOUT2
TQ
CLK
CLKDIV
D1 – D6
OCE
REV
SHIFTIN1
SHIFTIN2
SR
T1 to T4
TCE
Port Name
OSERDES Ports
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Data Path Output - OQ
3-state Control Output - TQ
High-Speed Clock Input - CLK
Divided Clock Input - CLKDIV
Table 8-6
The OQ port is the data output port of the OSERDES module. Data at the input port D1 will
appear first at OQ. This port connects the output of the data parallel-to-serial converter to
the data input of the IOB.
This port is the 3-state control output of the OSERDES module. When used, this port
connects the output of the 3-state parallel-to-serial converter to the control/3-state input of
the IOB.
This high-speed clock input drives the serial side of the parallel-to-serial converters.
This divided high-speed clock input drives the parallel side of the parallel-to-serial
converters. This clock is the divided version of the clock connected to the CLK port.
1 (each)
1 (each)
Width
1
1
1
1
1
1
1
1
1
1
1
1
lists the available ports in the OSERDES primitive.
Data path output. See
Carry out for data width expansion. Connect to SHIFTIN1 of master OSERDES.
See
Carry out for data width expansion. Connect to SHIFTIN2 of master OSERDES.
See
3-state control output. See
High-speed clock input. See
Divided clock input. Clocks delay element, deserialized data, Bitslip submodule,
and CE unit. See
Parallel data inputs. See
Output data clock enable. See
Reverse SR pin. Not available in the OSERDES block.
Carry input for data width expansion. Connect to SHIFTOUT1 of slave OSERDES.
See
Carry input for data width expansion. Connect to SHIFTOUT2 of slave OSERDES.
See
Active High reset.
Parallel 3-state inputs. See
3-state clock enable. See
OSERDES Width
OSERDES Width
OSERDES Width
OSERDES Width
www.xilinx.com
Divided Clock Input -
Expansion.
Expansion.
Expansion.
Expansion.
Data Path Output -
3-state Signal Clock Enable -
Parallel Data Inputs - D1 to
3-state Control Output -
Parallel 3-state Inputs - T1 to
High-Speed Clock Input -
Output Data Clock Enable -
Description
CLKDIV.
OQ.
TQ.
D6.
TCE.
CLK.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
T4.
OCE.
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