XC5VSX50T-1FF1136I Xilinx Inc, XC5VSX50T-1FF1136I Datasheet - Page 284
![IC FPGA VIRTEX-5 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX50T-1FF1136I
Manufacturer Part Number
XC5VSX50T-1FF1136I
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-1FF1136I
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
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Chapter 6: SelectIO Resources
X-Ref Target - Figure 6-76
284
DCI
SSTL2_II_T_DCI (2.5V) Split-Thevenin Termination
SSTL2_II_T_DCI
R 0 = 25
Ω
Figure 6-76: SSTL2_II_T_DCI (2.5V) Split-Thevenin Termination
Figure 6-76
SSTL2_II_T_DCI (2.5V) with on-chip split-Thevenin termination. In this bidirectional I/O
standard, when 3-stated, the termination is invoked on the receiver and not on the driver.
V
Not 3-stated
REF
= 1.25V
IOB
shows a sample circuit illustrating a valid termination technique for
Z 0
www.xilinx.com
3-stated
IOB
V
CCO
2R
2R
= 2.5V
VRP
VRN
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
V
REF
= 1.25V
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
SSTL2_II_T_DCI
ug190_6_92_041206
R 0 = 25
+
–
Ω
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