XC5VSX50T-1FF1136I Xilinx Inc, XC5VSX50T-1FF1136I Datasheet - Page 367
![IC FPGA VIRTEX-5 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX50T-1FF1136I
Manufacturer Part Number
XC5VSX50T-1FF1136I
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-1FF1136I
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- XC5VLX30-1FFG324C PDF datasheet
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X-Ref Target - Figure 8-11
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
1001 0011
(Repeating
Pattern)
SERDES_MODE=MASTER
BITSLIP_ENABLE = TRUE
BITSLIP_ENABLE = TRUE
D
D
SERDES_MODE=SLAVE
SHIFTOUT1 SHIFTOUT2
Figure 8-11: Circuit Diagram for Bitslip Configuration in 1:8 SDR Mode
SHIFTIN1
ISERDES
ISERDES
(Master)
(Slave)
Figure 8-11
to TRUE. Two ISERDES modules are in a master-slave configuration for a data width of
eight.
Guidelines for Using the Bitslip Submodule
Set the BITSLIP_ENABLE attribute to TRUE. When BITSLIP_ENABLE is set to FALSE, the
Bitslip pin has no effect. In a master-slave configuration, the BITSLIP_ENABLE attribute in
both modules must be set to TRUE.
To invoke a Bitslip operation, the BITSLIP port must be asserted High for one CLKDIV
cycle. In SDR mode, Bitslip cannot be asserted for two consecutive CLKDIV cycles; Bitslip
must be deasserted for at least one CLKDIV cycle between two Bitslip assertions. In both
SDR and DDR mode, the total latency from when the ISERDES captures the asserted
Bitslip input to when the “bit-slipped” ISERDES outputs Q1–Q6 are sampled into the
FPGA logic by CLKDIV is two CLKDIV cycles.
IOB
SHIFTIN2
(Q7)Q3
(Q8)Q4
BITSLIP
BITSLIP
illustrates the ISERDES configured in 1:8 SDR mode with Bitslip_ENABLE set
Q1
Q2
Q3
Q4
Q5
Q6
Q1
Q2
Q5
Q6
Initial
www.xilinx.com
1
0
0
1
0
0
1
1
Bitslip
1st
1
1
0
0
1
0
0
1
Input Serial-to-Parallel Logic Resources (ISERDES)
Bitslip
2nd
1
1
1
0
0
1
0
0
Bitslip
3th
0
1
1
1
0
0
1
0
Bitslip
4th
0
0
1
1
1
0
0
1
Bitslip
5th
1
0
0
1
1
1
0
0
Bitslip
Bitslip signal from system
6th
0
1
0
0
1
1
1
0
Bitslip
7th
0
0
1
0
0
1
1
1
8th Bitslip
(Back to initial)
1
0
0
1
0
0
1
1
ug190_8_11_100307
367
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