XC5VLX220T-1FFG1738C Xilinx Inc, XC5VLX220T-1FFG1738C Datasheet - Page 139

• Manufacturer Part Number: XC5VLX220T-1FFG1738C
• Description: IC FPGA VIRTEX-5 220K 1738FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX220T-1FFG1738C

• Total Ram Bits: 7815168
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Number Of I /o: 680
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1738-BBGA, FCBGA
• No. Of Logic Blocks: 17280
• No. Of Macrocells: 220000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 680
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Block RAM Retargeting
Table 4-12: Block RAM Retargeting
Built-in FIFO Support
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
RAMB16
True dual port
RAMB16
True dual port
RAMB16
Simple dual port
RAMB16
Simple dual port
CASC of two
RAMB16s
Primitive
Virtex-4 Block RAM
Multirate FIFO
Depth
1k to
16k
512
512
32k
Table 4-12
FPGA block RAM design in a new Virtex-5 FPGA design.
Many FPGA designs use block RAMs to implement FIFOs. In the Virtex-5 architecture,
dedicated logic in the block RAM enables users to easily implement synchronous or
multirate (asynchronous) FIFOs. This eliminates the need for additional CLB logic for
counter, comparator, or status flag generation, and uses just one block RAM resource per
FIFO. Both standard and first-word fall-through (FWFT) modes are supported.
In the Virtex-5 architecture, the FIFO can be configured as a 18 Kb or 36 Kb memory. For
the 18 Kb mode, the supported configurations are 4K x 4, 2K x 9, 1K x 18, and 512 x 36. The
supported configurations for the 36 Kb FIFO are 8K x 4, 4K x 9, 2K x 18, 1K x 36, and
512 x 72.
The block RAM can be configured as first-in/first-out (FIFO) memory with common or
independent read and write clocks. Port A of the block RAM is used as a FIFO read port,
and Port B is a FIFO write port. Data is read from the FIFO on the rising edge of read clock
and written to the FIFO on the rising edge of write clock. Independent read and write port
width selection is not supported in FIFO mode without the aid of external CLB logic.
The multirate FIFO offers a very simple user interface. The design relies on free-running
write and read clocks, of identical or different frequencies up to the specified maximum
frequency limit. The design avoids any ambiguity, glitch, or metastable problems, even
when the two frequencies are completely unrelated.
The write operation is synchronous, writing the data word available at DI into the FIFO
whenever WREN is active a set-up time before the rising WRCLK edge.
The read operation is also synchronous, presenting the next data word at DO whenever the
RDEN is active one set-up time before the rising RDCLK edge.
Port Width
1, 2, 4, 9, 18 RAMB18
Variable
36/36
36/36
R/W
1
suggests the most appropriate primitives to choose when mapping a Virtex-4
N/A
RAMB18
Simple dual port
Use closest
RAMB18 True
dual-port
N/A
Primitive
18k Virtex-5 Block RAM
www.xilinx.com
Depth
N/A
N/A
N/A
1k to
16k
512
Port Width
1, 2, 4, 9, 18 RAMB36
36/36
N/A
N/A
N/A
R/W
RAMB36
RAMB36
Simple dual port
Use closest
RAMB36 True
dual port
RAMB36
Primitive
36k Virtex-5 Block RAM
Block RAM Retargeting
Depth
N/A
2k to
32k
32k
1k
1k
Port Width
1, 2, 4, 9, 18
36/36
36/36
N/A
R/W
1
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