XC5VLX220T-1FFG1738C Xilinx Inc, XC5VLX220T-1FFG1738C Datasheet - Page 297

• Manufacturer Part Number: XC5VLX220T-1FFG1738C
• Description: IC FPGA VIRTEX-5 220K 1738FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX220T-1FFG1738C

• Total Ram Bits: 7815168
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Number Of I /o: 680
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1738-BBGA, FCBGA
• No. Of Logic Blocks: 17280
• No. Of Macrocells: 220000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 680
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Differential LVPECL (Low-Voltage Positive Emitter-Coupled Logic)
LVPECL Transceiver Termination
LVPECL is a very popular and powerful high-speed interface in many system applications.
Virtex-5 FPGA I/Os are designed to comply with the EIA/TIA electrical specifications for
2.5V LVPECL to make system and board design easier.
The Virtex-5 FPGA LVPECL transmitter and receiver requires the termination shown in
Figure
50 Ω transmission lines. The LVPECL driver is composed of two LVCMOS drivers that
form a compliant LVPECL output when combined with the three resistor output
termination circuit.
X-Ref Target - Figure 6-90
LVPECL_25
LVPECL_25
6-90, illustrating a Virtex-5 FPGA LVPECL transmitter and receiver on a board with
IOB
Figure 6-90: LVPECL Transmitter Termination
www.xilinx.com
70Ω
70Ω
R
R
S
S
R DIV
187Ω
Specific Guidelines for I/O Supported Standards
Z 0 = 50Ω
Z 0 = 50Ω
R DIFF = 100Ω
INX
IN
IOB
LVPECL_25
+
-
ug190_6_84_030506
Data in
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