XC5VLX220T-1FFG1738C Xilinx Inc, XC5VLX220T-1FFG1738C Datasheet - Page 85

• Manufacturer Part Number: XC5VLX220T-1FFG1738C
• Description: IC FPGA VIRTEX-5 220K 1738FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX220T-1FFG1738C

• Total Ram Bits: 7815168
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Number Of I /o: 680
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1738-BBGA, FCBGA
• No. Of Logic Blocks: 17280
• No. Of Macrocells: 220000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 680
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Fixed-Phase Shifting
In
in phase with the desired clock phase. The clock outputs are phase-shifted to appear
sometime later than the input clock, and the LOCKED signal is asserted.
X-Ref Target - Figure 2-18
•
Figure
Clock Event 1
Clock event 1 appears after the desired phase shifts are applied to the DCM. In this
example, the shifts are positive shifts. CLK0 and CLK2X are no longer aligned to
CLKIN. However, CLK0, and CLK2X are aligned to each other, while CLK90 and
CLK180 remain as 90° and 180° versions of CLK0. The LOCK signal is also asserted
once the clock outputs are ready.
2-18, the DCM outputs the correct frequency. However, the clock outputs are not
LOCKED
CLK180
CLK2X
CLK90
CLKIN
CLK0
Figure 2-18: Phase Shift Example: Fixed
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Lock Time
1
ug190_2_19_042406
DCM Timing Models
85