MPC859TVR133A Freescale Semiconductor, MPC859TVR133A Datasheet - Page 44

IC MPU POWERQUICC 133MHZ 357PBGA

MPC859TVR133A

Manufacturer Part Number
MPC859TVR133A
Description
IC MPU POWERQUICC 133MHZ 357PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC859TVR133A

Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
133MHz
Voltage
1.8V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Processor Series
MPC8xx
Core
MPC8xx
Data Bus Width
32 bit
Maximum Clock Frequency
133 MHz
Maximum Operating Temperature
+ 95 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
133MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 95C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC859TVR133A
Manufacturer:
MOTOLOLA
Quantity:
1 045
Part Number:
MPC859TVR133A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Bus Signal Timing
Table 14
44
R69
R70
R71
R72
R73
R74
R75
R76
R77
R78
R79
R80
R81
R82
Num
shows the reset timing for the MPC866/859.
CLKOUT to HRESET high impedance
(MAX = 0.00 x B1 + 20.00)
CLKOUT to SRESET high impedance
(MAX = 0.00 x B1 + 20.00)
RSTCONF pulse width (MIN = 17.00 x
B1)
Configuration data to HRESET rising
edge setup time (MIN = 15.00 x B1 +
50.00)
Configuration data to RSTCONF rising
edge setup time (MIN = 0.00 x B1 +
350.00)
Configuration data hold time after
RSTCONF negation (MIN = 0.00 x B1 +
0.00)
Configuration data hold time after
HRESET negation (MIN = 0.00 x B1 +
0.00)
HRESET and RSTCONF asserted to
data out drive (MAX = 0.00 x B1 +
25.00)
RSTCONF negated to data out high
impedance (MAX = 0.00 x B1 + 25.00)
CLKOUT of last rising edge before chip
three-states HRESET to data out high
impedance (MAX = 0.00 x B1 + 25.00)
DSDI, DSCK setup (MIN = 3.00 x B1)
DSDI, DSCK hold time (MIN = 0.00 x B1
+ 0.00)
SRESET negated to CLKOUT rising
edge for DSDI and DSCK sample (MIN
= 8.00 x B1)
Characteristic
MPC866/MPC859 Hardware Specifications, Rev. 2
Table 14. Reset Timing
515.20 —
504.50 —
350.00 —
0.00
0.00
90.90
0.00
242.40 —
Min
33 MHz
20.00 —
20.00 —
25.00 —
25.00 —
25.00 —
Max
425.00 —
425.00 —
350.00 —
0.00
0.00
75.00
0.00
200.00 —
Min
40 MHz
20.00 —
20.00 —
25.00 —
25.00 —
25.00 —
Max
340.00 —
350.00 —
350.00 —
0.00
0.00
60.00
0.00
160.00 —
Min
50 MHz
20.00 —
20.00 —
25.00 —
25.00 —
25.00 —
Max
257.60 —
277.30 —
350.00 —
0.00
0.00
45.50
0.00
121.20 —
Freescale Semiconductor
Min
66 MHz
20.00 ns
20.00 ns
25.00 ns
25.00 ns
25.00 ns
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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