MPC859TVR133A Freescale Semiconductor, MPC859TVR133A Datasheet - Page 61

• Manufacturer Part Number: MPC859TVR133A
• Description: IC MPU POWERQUICC 133MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC859TVR133A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 133MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 133 MHz
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.7 SCC in NMSI Mode Electrical Specifications
Table 22
Table 23
Freescale Semiconductor
1
2
1
2
Num
100
102
103
104
105
106
107
108
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1.
Also applies to CD and CTS hold time when they are used as an external sync signals.
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1.
Also applies to CD and CTS hold time when they are used as an external sync signal.
Num
100
101
102
103
104
105
106
107
108
shows the NMSI external clock timings.
shows the NMSI internal clock timings.
RCLK1 and TCLK1 frequency
RCLK1 and TCLK1 rise/fall time
TXD1 active delay (from TCLK1 falling edge)
RTS1 active/inactive delay (from TCLK1 falling edge)
CTS1 setup time to TCLK1 rising edge
RXD1 setup time to RCLK1 rising edge
RXD1 hold time from RCLK1 rising edge
CD1 setup time to RCLK1 rising edge
RCLK1 and TCLK1 width high
RCLK1 and TCLK1 width low
RCLK1 and TCLK1 rise/fall time
TXD1 active delay (from TCLK1 falling edge)
RTS1 active/inactive delay (from TCLK1 falling edge)
CTS1 setup time to TCLK1 rising edge
RXD1 setup time to RCLK1 rising edge
RXD1 hold time from RCLK1 rising edge
CD1 setup time to RCLK1 rising edge
MPC866/MPC859 Hardware Specifications, Rev. 2
Table 22. NMSI External Clock Timings
Table 23. NMSI Internal Clock Timings
Characteristic
Characteristic
1
1
2
2
1/SYNCCLK +5
1/SYNCCLK
All Frequencies
40.00
40.00
40.00
0.00
0.00
0.00
0.00
Min
0.00
0.00
5.00
5.00
5.00
5.00
Min
—
—
All Frequencies
CPM Electrical Characteristics
SYNCCLK/3
30.00
30.00
Max
—
—
—
—
—
15.00
50.00
50.00
Max
—
—
—
—
—
—
Unit
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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