XS1-G04B-FB512-C4 XMOS, XS1-G04B-FB512-C4 Datasheet
XS1-G04B-FB512-C4
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XS1-G04B-FB512-C4 Summary of contents
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... XS1-G4 512BGA Datasheet Publication Date: 2010/06/07 Copyright © 2010 XMOS Ltd. All Rights Reserved. Version 3.5 ...
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... XMOS chips are general-purpose programmable devices that can be used in a wide range of applications and systems. The XS1-G4 device integrates four XCore™ de- vices. Each XCore contains a 32-bit processor, SRAM memory, I/O ports for communicating with external components and channels for com- municating with other devices ...
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... XS1-G4 512BGA Datasheet (3.5) 1 Signal Descriptions This section describes the external signal pins of the XS1-G4 in the 512BGA package. The following I/O type conventions are used in this document 1.1 XCore Signals XCore signals can be used for generic I/O ports or for XMOS Links. All the XCore ...
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... XS1-G4 512BGA Datasheet (3.5) 1.1.2 XCore signals as XMOS Links XMOS Links are full duplex and may operate in either 5wire/direction or 2wire/direc- tion mode. See Section 1.2 5wire fast mode The following table shows the XMOS link fast interface allocation on each XCore processor: ...
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... XS1-G4 512BGA Datasheet (3.5) 1.1.3 Precedence Ports and XMOS Links are connected to pins on the XS1-G4 by the program running on the device. The ports and links are multiplexed and follow a defined precedence if they overlap on the same core XMOS Link is enabled, the link has access to the pins; the pins of the underlying ports are disabled ...
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... XS1-G4 512BGA Datasheet (3.5) 1.2 Port Pin Table XCORES Package Ball Location Ball Name XnD0 M6 N6 N19 M19 XnD1 M5 N5 N20 M20 XnD2 L6 P6 P19 L19 XnD3 L5 P5 P20 L20 XnD4 K6 R6 R19 K19 XnD5 K5 R5 R20 K20 XnD6 J6 T6 T19 ...
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... XS1-G4 512BGA Datasheet (3.5) 1.3 System Service Pin Table Signal Ball ID SS_BYPASS_PLL_LOCK G9 SS_CLK H7 SS_DEBUG M18 SS_EXT_OSC_CONFIG M7 SS_EXT_OSC_HS_MODE N7 SS_PLL_BYPASS G8 SS_RESET G12 SS_TCK U18 1.4 Core Power and Ground Pin Table Signal Ball ID VDD G10 VDD G11 VDD G14 VDD G15 VDD G16 ...
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... XS1-G4 512BGA Datasheet (3.5) 1.5 XCore I/O Power Table Signal Ball ID IO VDD A1 IO VDD A2 IO VSS A6 IO VDD A10 IO VSS A15 IO VDD A19 IO VSS A23 IO VSS A24 IO VDD B1 IO VDD B2 IO VSS B6 IO VDD B10 IO VSS B15 IO VDD B19 IO VSS ...
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... XS1-G4 512BGA Datasheet (3.5) 2 System Services System Services are required to support correct device behavior. These signals control clocking, reset and boot behavior of the device. 2.1 Clock control signals These signals control the PLL of the XS1-G4 Signal Ball ID SS_EXT_OSC_CONFIG M7 SS_EXT_OSC_HS_MODE N7 SS_PLL_BYPASS G8 SS_BYPASS_PLL_LOCK ...
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... The boot status pins are dual function. Prior to reset, bits 1:0 function as inputs prior to the de-assertion of reset. The XS1-G4 latches the value driven on these two pins on the rising edge (de-assertion) of SS_RESET. The value driven should be static and configured using pullup or pulldown resistors, as the XS1-G4 drives the boot status on these pins after reset. The value confi ...
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... For further details on booting XCores see the XS1-G System Specification document (http://xmos.com/published/xsystem). SS_DEBUG This pin is used to synchronize the debugging of multiple G4 devices. This pin can operate in both output and input mode. In output mode and when configured to do so, SS_DEBUG is driven low by the device when one or more internal XCore processors hit a debug break point. Prior to this point the pin is tri-stated. In input mode and when confi ...
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... XS1-G4 512BGA Datasheet (3.5) 2.3 JTAG Operation The XS1-G family supports a generic 5pin JTAG interface, which can be used to provide hardware testing including: Boundary scan testing for correct board connectivity Onboard source level debugging from remote terminals Boundary scanning for OTP ROM ...
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... XS1-G4 512BGA Datasheet (3.5) Register Number DEVICE_ID0 0x00 DEVICE_ID1 0x01 DEVICE_ID2 0x02 DEVICE_ID3 0x03 DBG_CTRL 0x04 DBG_INT 0x05 PLL_CLK_DIVIDER 0x06 SECURITY_CONFIG 0x07 PLINK[3:0] 0x10 : 0x13 DBG_SCRATCH[7:0] 0x20 : 0x27 T[7:0]_PC 0x40 : 0x47 T[7:0]_SR 0x60 : 0x67 The JTAG controller can read from the DBG_SCRATCH registers at the same time as the XCore, but if both devices write at the same time, the XCore write completes and the JTAG controller is ignored ...
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... XS1-G4 512BGA Datasheet (3. and Switching Characteristics 3.1 Operating Conditions Symbol Parameter IO_VDD I/O DC supply voltage VDD Core DC supply voltage SS_PLL_AVDD PLL analogue supply SS_PLL_DVDD PLL Digital DC Supply SS_OTP_VPP OTP external programming voltage Cl XCore I/O load capacitance Operating range (Commercial) Ta Operating range (Industrial) ...
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... XS1-G4 512BGA Datasheet (3.5) 2. Voltages with respect to IO VSS 3. Internal pull-up resistors are fitted to general purpose XCore I/O pins. Applies to both XCore I/O and XCore link I/Os. 4. Use for unused I/O only—the internal pull up resistor is not recommended as a substitute for an external pull-up resistor. ...
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... Consumption For XS1-G Devices Application Note 3.6 Clock XS1-G devices use an input clock frequency, supplied by the user on the SS_CLK pin, to drive the PLL and obtain the system clock. The nominal frequency of the clock for all XS1 family components is 20MHz but other clock frequencies can be derived from SS_CLK using the MODE pins and internal PLL ...
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... Memory 3.7.1 Internal static memory The XS1-G4 has a total of 256K bytes of fast internal static memory for high rates of data throughput, divided into 64k bytes per XCore. Each internal memory access consumes one core clock cycle. There is no dedicated external memory interface, although memory can be expanded through appropriate use of the ports ...
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... ClkBlk The Input Valid window parameter relates to the capability of the XS1-G4 family devices to capture data input to the chip with respect to an external clock source. This parameter can be calculated as the sum of the input setup time and input hold time with regard to the external clock as measured at the G4 device pins. The output invalid window specifi ...
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... XS1-G4 512BGA Datasheet (3.5) 3.10 JTAG Timing The JTAG interface may be operated in either synchronous or asynchronous mode. Parameters SS_TCLK period TSU TH TCO Notes: 1. Timing applies to SS_TMS, SS_TRST, SS_TDI inputs 2. Timing applies to SS_TDO output 4 Package Details 4.1 Package Pin Layout The following diagrams show the ball name and location for the BGA512 Package. ...
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... XS1-G4 512BGA Datasheet (3.5) Pin layout VDD IO VDD X0D61 X0D63 X0D65 IO VSS X0D67 X0D69 SPAR B IO VDD IO VDD X0D62 X0D64 IO VSS X0D66 X0D68 X0D70 E SPAR C X0D58 IO VDD X0D37 X0D39 X0D41 IO VSS E D X0D57 X0D56 X0D35 IO VDD X0D36 X0D38 X0D40 E X0D55 X0D54 X0D33 X0D34 ...
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... XS1-G4 512BGA Datasheet (3.5) 4-bit and 1-bit ports VDD IO VDD X0D61 X0D63 X0D65 IO VSS X0D67 B IO VDD IO VDD SPARE IO VSS X0D62 X0D64 X0D66 C SPARE IO VDD IO VSS X0D58 P1N0 P1P0 X0D41 D X0D57 X0D56 P1L0 IO VDD P1M0 P1O0 X0D40 E IO VDD X0D55 X0D54 ...
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... XS1-G4 512BGA Datasheet (3.5) 8-bit and 1-bit ports VDD IO VDD X0D61 X0D63 X0D65 IO VSS X0D67 B IO VDD IO VDD SPARE IO VSS X0D62 X0D64 X0D66 C SPARE IO VDD IO VSS X0D58 P8D1 P8D3 P8D5 D X0D57 X0D56 P1L0 IO VDD P8D0 P8D2 P8D4 E IO VDD X0D55 X0D54 ...
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... XS1-G4 512BGA Datasheet (3.5) 16-bit and 1-bit ports VDD IO VDD X0D61 X0D63 X0D65 IO VSS X0D67 B IO VDD IO VDD SPARE IO VSS X0D62 X0D64 X0D66 C SPARE IO VDD P16B9 P16B11 P16B13 IO VSS P16B15 SPARE SPARE IO VDD SPARE SPARE IO VSS SPARE SPARE P16B15 IO VDD P16B13 P16B11 P16B9 ...
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... XS1-G4 512BGA Datasheet (3.5) 32-bit and 1-bit ports VDD IO VDD P32A10 P32A12 P32A14 IO VSS P32A16 P32A18 SPARE IO VDD SPARE SPARE SPARE SPARE IO VSS SPARE P32A18 P32A16 IO VDD P32A14 P32A12 P32A10 IO VSS IO VSS B IO VDD IO VDD SPARE P32A11 P32A13 IO VSS P32A15 P32A17 P32A19 IO VDD SPARE SPARE SPARE SPARE IO VSS P32A19 P32A17 P32A15 IO VDD P32A13 P32A11 SPARE IO VSS IO VSS ...
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... XS1-G4 512BGA Datasheet (3.5) 5bit XMOS Links VDD IO VDD XLD4out XLD2out XLD0out IO VSS XLD1in XLD3in SPARE IO VDD SPARE SPARE SPARE SPARE IO VSS SPARE XLD3out XLD1out IO VDD XLD0in XLD2in XLD4in IO VSS IO VSS B IO VDD IO VDD SPARE XLD3out XLD1out IO VSS XLD0in XLD2in XLD4in IO VDD SPARE SPARE SPARE SPARE IO VSS XLD4out XLD2out XLD0out IO VDD XLD1in XLD3in SPARE IO VSS IO VSS ...
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... XS1-G4 512BGA Datasheet (3.5) 2bit XMOS Links VDD IO VDD X0D61 X0D63 XLD0out IO VSS XLD1in B IO VDD IO VDD SPARE X0D62 XLD1out IO VSS XLD0in C SPARE IO VDD X0D37 IO VSS X0D58 X0D39 X0D41 D X0D57 X0D56 X0D35 IO VDD X0D36 X0D38 X0D40 E IO VDD X0D13 X0D15 XLB0out IO VSS XLB1in ...
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... XS1-G4 512BGA Datasheet (3.5) 4.2 Package Mechanical Details Dimensional Ref REF Min Nom Max A 1.6 A1 0.27 A2 1.02 1.06 1.1 D 20.0 D1 18.4 E 20.0 E1 18.4 b 0.5 c 0.32 0.36 0.40 e 0 512 Dimensional Tol aaa 0.15 1. All dimensions in mm. 2. ‘e’ represents the basic solder ball pitch. ...
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... XS1-G4 512BGA Datasheet (3.5) 5 Device Configuration Example schematic diagrams detailing minimal system configurations may be found at: http://xmos.com/support/silicon 6 Device ID 6.1 XMOS JEDEC Manufacturer ID JEDEC is an international organization that manages standards in the electronic and semiconductor industries. XMOS has a unique Manufacturers ID which is: ...
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... XMOS Ident & Architecture Family (G general purpose) XCore Tiles Revision Mask (A-Z) Package Type Pin Count Temp Grade (C commercial 0-70C) Speed Grade (4 normal speed) 7.1 Orderable part numbers Part Number XS1-G04B-FB512-C4 XS1-G04B-FB512-I4 XS1 Package PBGA512 0.8mm pitch PBGA512 0.8mm pitch www.xmos.com 29/30 ...
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... Programming XC on XMOS Devices XS1-G System Specification XMOS Tools User Guide XS1 Assembly Language Manual XMOS XS1 32-Bit Application Binary Interface XS1-G Clock Frequency Control Application Note Estimating Power Consumption For XS1-G Devices Document History Date Release 2009-12-18 3.4 2010-06-07 3 ...