XS1-G04B-FB512-C4 XMOS, XS1-G04B-FB512-C4 Datasheet - Page 10

• Manufacturer Part Number: XS1-G04B-FB512-C4
• Description: IC MPU 32BIT QUAD CORE 512FBGA
• Manufacturer: XMOS

Specifications of XS1-G04B-FB512-C4

• Processor Type: XCore 32-Bit
• Speed: 1600MIPS
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 512-BGA
• For Use With: XMOS AVB REF KIT - KIT REF AVB W/4 XS1-G-DK880-1016 - KIT REF LED RGB 16X32 W/XC-3880-1015 - BOARD KIT XS1-G4 LED CTRL TILE880-1014 - BOARD DEV KIT XS1-G4 ETHERNET880-1013 - BOARD DEV KIT XS1-G4880-1012 - KIT DEV 4CORE G4 W/LCD TOUCH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1010

XS1-G4 512BGA Datasheet (3.5)
SS_PLL_AVDD The on-chip PLL requires a very clean AVDD power supply. It is
SS_PLL_AGND Analogue ground for the PLL. Connect directly to board ground.
SS_CLK Reference clock signal for the on-chip PLL. A default frequency of 20MHz is
2.2 Miscellaneous control signals
Functional description
SS_XC0_BS[3:0], SS_XC1_BS[3:0] Boot status pins.
Signal
SS_XC0_BS[3:0]
SS_XC1_BS[3:0]
SS_DEBUG
SS_RESET
SS_XC0_CFG[1:0]
SS_TEST_ENA
SS_RESERVED
recommended that this supply node be separated from the other, noisier,
supplies in the board. The supply should be decoupled close to the respective
IC power pins. Nominally 1.0V.
typically used by XS1 family devices. However other frequencies can be derived
from SS_CLK using the SS_EXT_OSC_CONFIG and SS_EXT_OSC_HS_MODE pins.
Clock frequencies of
The boot status pins are dual function.
Prior to reset, bits 1:0 function as inputs prior to the de-assertion of reset.
The XS1-G4 latches the value driven on these two pins on the rising edge
(de-assertion) of SS_RESET. The value driven should be static and configured
using pullup or pulldown resistors, as the XS1-G4 drives the boot status on
these pins after reset. The value configured on these two pins defines the boot
mode for XCore 0 as follows:
Value
00
01
10
11
Ball ID
P23, N23,
J18, H18
P24,
N24,M24,
L24
M18
G12
M23, L23
T18
20 MHz and
I/O
IO, PU
IO, PU
IO, PU, ST
I, PD, ST
I, PD
I, PD
www.xmos.com
25 MHz are supported.
Description
Reserved
Reserved
Boot from SPI
Boot from JTAG
XCore0
XCore1
Function Description
Boot
status
Boot
Status
Debug
Reset
See Boot status pins below
See Boot status pins below
Activates multicore debug
Asynchronous system reset
Reserved, tie to IO_VDD
Reserved, tie pin to ground
Reserved, leave unconnected
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