MPC8360EVVAJDGA Freescale Semiconductor, MPC8360EVVAJDGA Datasheet - Page 18

• Manufacturer Part Number: MPC8360EVVAJDGA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8360EVVAJDGA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8360E-RDK
• Maximum Clock Frequency: 533 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 740
• Rohs Compliant: Yes
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RESET Initialization
5.2
This section describes the AC electrical specifications for the reset initialization timing requirements of
the device.
component(s).
18
Output low voltage
Notes:
1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.
2. HRESET and SRESET are open drain pins, thus V
Required assertion time of HRESET or SRESET (input) to activate reset flow
Required assertion time of PORESET with stable clock applied to CLKIN
when the device is in PCI host mode
Required assertion time of PORESET with stable clock applied to
PCI_SYNC_IN when the device is in PCI agent mode
HRESET/SRESET assertion (output)
HRESET negation to SRESET negation (output)
Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the device is
in PCI host mode
Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the device is
in PCI agent mode
Input hold time for POR config signals with respect to negation of HRESET
Time for the device to turn off POR config signals with respect to the
assertion of HRESET
Time for the device to turn on POR config signals with respect to the negation
of HRESET
Notes:
1. t
2. t
3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for more details.
MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for more details.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
PCI_SYNC_IN
CLKIN
is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the
RESET AC Electrical Characteristics
Table 11
is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
Characteristic
provides the reset initialization AC timing specifications for the DDR SDRAM
Table 10. RESET Pins DC Electrical Characteristics (continued)
Parameter/Condition
Table 11. RESET Initialization Timing Specifications
OH
is not relevant for those pins.
Symbol
V
OL
I
OL
Condition
= 3.2 mA
Min
512
32
32
32
16
—
4
4
0
1
Max
—
—
—
—
—
—
—
—
—
4
Min
—
Freescale Semiconductor
t
t
t
t
t
t
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
t
t
CLKIN
CLKIN
Unit
ns
ns
Max
0.4
Notes
1, 3
Unit
1
2
1
1
1
2
1
3
V