MPC8360EVVAJDGA Freescale Semiconductor, MPC8360EVVAJDGA Datasheet - Page 35

• Manufacturer Part Number: MPC8360EVVAJDGA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8360EVVAJDGA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8360E-RDK
• Maximum Clock Frequency: 533 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 740
• Rohs Compliant: Yes
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.2.3.2
Table 32
Figure 16
Figure 17
Freescale Semiconductor
At recommended operating conditions with LV
REF_CLK clock period
REF_CLK duty cycle
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
REF_CLK clock rise time
REF_CLK clock fall time
Note:
1. The symbols used for timing specifications follow the pattern of t
inputs and t
receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. Also, t
the time data input signals (D) went invalid (X) relative to the t
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of t
convention is used with the appropriate letter: R (rise) or F (fall).
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
provides the RMII receive AC timing specifications.
provides the AC test load.
shows the RMII receive AC timing diagram.
(first two letters of functional block)(reference)(state)(signal)(state)
RMII Receive AC Timing Specifications
REF_CLK
RXD[1:0]
CRS_DV
Parameter/Condition
RX_ER
Output
Table 32. RMII Receive AC Timing Specifications
Figure 17. RMII Receive AC Timing Diagram
t
RMRDVKH
t
RMXH
DD
/OV
RMX
DD
t
RMX
represents the RMII (RM) reference (X) clock. For rise and fall times, the latter
Z
Figure 16. AC Test Load
of 3.3 V ± 10%.
0
= 50 Ω
Valid Data
RMRDXKL
RMX
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
t
RMXF
t
RMXH
t
t
Symbol
RMRDXKH
(first three letters of functional block)(signal)(state)(reference)(state)
RMRDVKH
for outputs. For example, t
t
t
clock reference (K) going to the low (L) state or hold time.
t
RMXR
RMXF
RMX
/t
symbolizes RMII receive timing (RMR) with respect to
RMX
1
R
t
RMRDXKH
L
t
RMXR
= 50 Ω
Min
4.0
2.0
1.0
1.0
35
—
LV
DD
RMRDVKH
/2
Typ
20
—
—
—
—
—
symbolizes RMII
Max
4.0
4.0
65
—
—
—
RMX
clock
Unit
ns
ns
ns
ns
ns
%
for
35