MPC8360EVVAJDGA Freescale Semiconductor, MPC8360EVVAJDGA Datasheet - Page 88

• Manufacturer Part Number: MPC8360EVVAJDGA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8360EVVAJDGA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8360E-RDK
• Maximum Clock Frequency: 533 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 740
• Rohs Compliant: Yes
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocking
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
frequency.
Table 69
conditions (see
Maximum operating frequencies depend on the part ordered, see
Addressed by this Document,”
authorized distributor for more information.
1
2
3
4
5
88
e300 core frequency ( core_clk )
Coherent system bus frequency ( csb_clk )
QUICC Engine frequency
DDR and DDR2 memory bus frequency (MCLK)
Local bus frequency (LCLK n )
PCI input frequency (CLKIN or PCI_CLK)
Security core maximum internal operating frequency
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk , MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
The 667 MHz core frequency is based on a 1.3 V V
The 500 MHz QE frequency is based on a 1.3 V V
The DDR data rate is 2x the DDR memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2× the
csb_clk frequency (depending on RCWL[LBCM]).
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
provides the operating frequencies for the TBGA package under recommended operating
Table
1
Security core
PCI and DMA complex
Characteristic
With limitation, only for slow csb_clk rates, up to 166 MHz.
3
2). All frequency combinations shown in the table below may not be available.
( ce_clk )
5
Table 69. Operating Frequencies for the TBGA Package
Unit
1
for part ordering details and contact your Freescale sales representative or
Table 68. Configurable Clock Units
4
Table 68
DD
DD
Frequency
supply voltage.
csb_clk
supply voltage.
Default
csb_clk
400 MHz
266–400
specifies which units have a configurable clock
133
/3
Off,
csb_clk
Off,
csb_clk
csb_clk
Section 25.1, “Part Numbers Fully
/3
100–166.67
16.67–133
25–66.67
533 MHz
266–533
133–333
266–500
1
133
Options
, csb_clk
/2,
667 MHz
Freescale Semiconductor
266–667
166
2
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit