MPC8260AZUPIBB Freescale Semiconductor, MPC8260AZUPIBB Datasheet - Page 4

• Manufacturer Part Number: MPC8260AZUPIBB
• Description: IC MPU POWERQUICC II 480-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of MPC8260AZUPIBB

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 300MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 480-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 300MHz
• Embedded Interface Type: I2C, MII, SPI, TDM, UTOPIA
• Digital Ic Case Style: TBGA
• No. Of Pins: 480
• Rohs Compliant: No
• For Use With: MPC8260ADS-TCOM - BOARD DEV ADS POWERQUICC II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Features
4
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
— Interfaces to G2 core through on-chip 24-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers (two on the MPC8255) supporting the following
— Two multichannel controllers (MCCs) (only MCC2 on the MPC8255)
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
— Two serial management controllers (SMCs), identical to those of the MPC860
— One serial peripheral interface identical to the MPC860 SPI
— One inter-integrated circuit (I
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
for communications protocols
protocols:
– 10/100-Mbit Ethernet/IEEE Std 802.3™ CDMA/CS interface through media independent
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1,
– Transparent
– HDLC—Up to T3 rates (clear channel)
– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
– Transparent
– UART (low-speed operation)
– Microwire compatible
– Multiple-master, single-master, and slave modes
interface (MII)
AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external
connections
into four subgroups of 32 channels each.
interfaces up to four TDM interfaces per MCC
division-multiplexed (TDM) channels
2
C) controller (identical to the MPC860 I
2
C controller)
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