668-0003-C Rabbit Semiconductor, 668-0003-C Datasheet - Page 100

• Manufacturer Part Number: 668-0003-C
• Description: IC CPU RABBIT2000 30MHZ 100PQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 668-0003-C

• Rohs Status: RoHS non-compliant
• Processor Type: Rabbit 2000 8-Bit
• Speed: 30MHz
• Voltage: 2.7V, 3V, 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Features: -
• Other names: 316-1004; 668-0003

8.3 Memory Control Unit Registers
The Memory Bank Control Registers manage the physical memory space for the Rabbit
2000. There are four memory banks, where each bank is selected by the two most signifi-
cant bits of the 20-bit physical memory address. Each memory bank can be programmed to
have zero, one, two, or four wait states added automatically, and writes can be disabled or
enabled for each bank. The Rabbit 2000 chip has three memory chip selects, two memory
output enables, and two memory write enables. Any of these signals can be selected for
any memory bank. The final option available for each memory bank is to invert either or
both of the two most significant address bits while accessing a memory bank. This allows
each bank to contain four 256K byte pages, only one of which is available at a time.
In revisions A–C of the Rabbit 2000 chip, the reset state of the MB0CR register is set to
inhibit /WE0. See Section B.2.6 for more information.
8.3.1 Memory Bank Control Registers
Table 8-3 describes the operation of the four memory bank control registers. The registers
are write-only. Each register controls one quadrant in the 1M address space.
• Bits 7,6—The number of wait states used in access to this quadrant. Without wait
• Bits 5, 4—These bits allow the upper address lines to be inverted. This inversion occurs
• Bit 3—Inhibits the write pulse to memory accessed in this quadrant. Useful for protect-
• Bit 2—Selects which set of the two lines /OEx and /WEx will be driven for memory
• Bits 1,0—Determines which of the three chip select lines will be driven for memory
• All bits of the control register are initialized to zero on reset.
94
00—4 wait states
01—2 wait states
10—1 wait states
11—0 wait states
states, read requires 2 clocks and write requires 3 clocks. The wait state adds to these
numbers. Wait states should only be used for memory data accesses (RAM or data
flash), not for memory from which instructions are executed (code memory).
after the logic that selects the bank register, so setting these lines has no effect on which
bank register is used. The inversion may be used to install a 1M memory chip in the
space normally allocated to a 256K chip. The larger memory can then be accessed as 4
pages of 256K each. There is no effect outside the quadrant that the memory bank con-
trol register is controlling.
ing flash memory from an inadvertent write pulse, which will not actually write to the
flash because it is protected by lock codes, but will temporarily disable the flash mem-
ory and crash the system if the memory is used for code.
accesses in this quadrant.
accesses to this quadrant.
Bits 7,6
Table 8-3. Memory Bank Control Register x (MBxCR = 0x14+x)
1—Invert
address
A19
Bit 5
1—Invert
address
A18
Bit 4
1—Write-
protect memory
this quadrant
Bit 3
Rabbit 2000 Microprocessor User’s Manual
0—use /OE0, /WE0
1—use /OE1, /WE1
Bit 2
00—use /CS0
01—use /CS1
1x—use /CS2
Bits 1,0