668-0003-C Rabbit Semiconductor, 668-0003-C Datasheet - Page 220

• Manufacturer Part Number: 668-0003-C
• Description: IC CPU RABBIT2000 30MHZ 100PQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 668-0003-C

• Rohs Status: RoHS non-compliant
• Processor Type: Rabbit 2000 8-Bit
• Speed: 30MHz
• Voltage: 2.7V, 3V, 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Features: -
• Other names: 316-1004; 668-0003

B.2.10 DDCB/FDCB Instruction Page and Wait State Bug Fixes
Four-byte instructions starting with DD-CB or FD-CB didn't work when attempted with
wait states.
The fetch of the byte immediately following the instruction did not have the correct num-
ber of wait states inserted for the following instructions only when using wait states.
Rather than the programmed number of wait states, the fetch was short by one wait state.
A similar thing happens for the block move instructions. In these cases, the read cycle is
short by one wait state.
For the multiply instruction, the fetch of the first byte after the MUL instruction had no
wait states, independent of the number programmed.
These problems were corrected in revisions A–C of the Rabbit 2000.
New Bug with LDIR/LDDR
A new LDIR/LDDR bug was discovered in September, 2002. The problem has to do with
wait states and the block move operations. With this problem, the first iteration of
LDIR/LDDR
ever, all subsequent iterations use the number of waits programmed for the memory
located at the write address for both the read and write cycles. This becomes a problem
when moving a block of data from a slow memory device requiring wait states to a fast
memory device requiring no wait states. With respect to external I/O operations, the
or
I/O for all but the first iteration. The first iteration is correct. This bug is automatically cor-
rected by Dynamic C.
B.2.11 LDIR/LDDR Instruction/Data Split Bug Fix
The bug with
do with the way the memory control unit treated the move from and the move to addresses
of the block move operation. With the instruction/data split enabled, data access in the
ROOT and/or DATASEG regions would result in addresses A16 and/or A19 being
inverted, depending on how the MMIDR was configured. This would allow the data space
to be moved up or down by 64K or 512 K.
With this problem, the first iteration of
sion for data accesses in the ROOT and/or DATASEG regions. However, all subsequent
iterations took place in the code region (without any address inversion).
This problem was fixed in revisions B and C of the Rabbit 2000.
214
LDDR
DJNZ (branch not taken only)
JR cc (branch not taken only)
JP cc (branch not taken only)
LDDR
LDIR
performs reads with zero wait states independent of the waits programmed for the
uses the correct number of wait states for both the read and the write. How-
LDIR
/
LDDR
and separate I & D space discovered in the Rabbit 2000A had to
LDIR
/
LDDR
resulted in the correct address inver-
Rabbit 2000 Microprocessor User’s Manual
LDIR