668-0003-C Rabbit Semiconductor, 668-0003-C Datasheet - Page 121

• Manufacturer Part Number: 668-0003-C
• Description: IC CPU RABBIT2000 30MHZ 100PQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 668-0003-C

• Rohs Status: RoHS non-compliant
• Processor Type: Rabbit 2000 8-Bit
• Speed: 30MHz
• Voltage: 2.7V, 3V, 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Features: -
• Other names: 316-1004; 668-0003

11.2 Timer B
Figure 11-1 shows a block diagram of Timer B.
The main clock for Timer B is
/2. Bit 0 of the TBCSR register controls the main clock
PCLK
for Timer B. The Timer B counter can be driven directly by
/2,
/16 [(
/2)/8],
PCLK
PCLK
PCLK
or by the output of Timer A1. The first two options are controlled by bit 0 in TBCSR. The
third option has to be enabled or disabled through bit 0 of the TACSR register.
Timer B has a continuously running 10-bit counter. The counter is compared against two
match registers, the B1 match register and the B2 match register. When the counter transi-
tions to a value equal to a match register, an internal pulse with a length of 1 peripheral
clock is generated. The match pulse can be used to cause interrupts and/or clock the output
registers of parallel ports D and E.
There are two ways to set up the Timer B match registers for use, one just after power-up,
and one for after using the Timer B match register system.
After power-up or reset, the value in the TBLxR match register is flagged as "invalid." At
this time a value written to the holding register will be transferred to the match register on
the next rising edge of the Timer B clock. Once the value is loaded in the match register,
an internal flag will indicate that a valid value is present in the match register. If another
value is written to the same register, it will stay in the holding register. Once a match
occurs, the value in the TBLxR match register is flagged as “invalid.” At that time, if a
value is in the holding register, it will get transferred to the match register, assuming that
the Timer B clock is running.
Every time a match condition occurs, the processor sets an internal bit that marks the match
value in TBLxR as invalid. Reading TBCSR clears the interrupt condition. TBLxR must
be reloaded to re-enable the interrupt. TBMxR does not need to be reloaded every time.
If both match registers need to be changed, the most significant byte needs to be changed first.
Chapter 11 Timers
115