Z84C2008PEG Zilog, Z84C2008PEG Datasheet - Page 155
![IC 8MHZ Z80 CMOS PIO 40-DIP](/photos/6/57/65796/269-40-dip_sml.jpg)
Z84C2008PEG
Manufacturer Part Number
Z84C2008PEG
Description
IC 8MHZ Z80 CMOS PIO 40-DIP
Manufacturer
Zilog
Series
Z80r
Specifications of Z84C2008PEG
Processor Type
Z80
Features
Low Power CMOS
Speed
8MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z84C2xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Base Number
84
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z84C2008PEG
Manufacturer:
Zilog
Quantity:
20
- Current page: 155 of 308
- Download datasheet (2Mb)
Operation:
Op Code:
Operands:
Description: The contents of the memory location addressed by the HL register pair is
Condition Bits Affected:
UM008005-0205
A-(HL), HL ← HL+1, BC ← BC-1
CPIR
—
compared with the contents of the Accumulator. In case of a true compare, a
condition bit is set. HL is incremented and the Byte Counter (register pair
BC) is decremented. If decrementing causes BC to go to zero or if A = (HL),
the instruction is terminated. If BC is not zero and A ≠ (HL), the program
counter is decremented by two and the instruction is repeated. Interrupts are
recognized and two refresh cycles are executed after each data transfer.
If BC is set to zero before instruction execution, the instruction loops
through 64 Kbytes if no match is found.
For BC ≠ 0 and A ≠ (HL):
For BC = 0 and A = (HL):
S is set if result is negative; reset otherwise
Z is set if A equals (HL); reset otherwise
H is set if borrow from bit 4; reset otherwise
P/V is set if BC -1 does not equal 0; reset otherwise
N is set
C is not affected
1
1
1
0
M Cycles
M cycles
1
1
5
4
0
1
1
0
21 (4, 4, 3, 5, 5)
CPIR
16 (4, 4, 3, 5)
1
0
T States
T States
0
0
1
1
ED
B1
4 MHz E.T.
4 MHz E.T.
5.25
4.00
Z80 Instruction Set
User’s Manual
Z80 CPU
135
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