Z84C2008PEG Zilog, Z84C2008PEG Datasheet - Page 45

• Manufacturer Part Number: Z84C2008PEG
• Description: IC 8MHZ Z80 CMOS PIO 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C2008PEG

• Processor Type: Z80
• Features: Low Power CMOS
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z84C2xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z80 CPU
User’s Manual
25
instruction such as a 3-byte call to any location in memory could be
executed.
The number of clock cycles necessary to execute this instruction is two
more than the normal number for the instruction. This occurs because the
CPU automatically adds two wait states to an Interrupt response cycle to
allow sufficient time to implement an external daisy-chain for priority
control. Figure 9 and Figure 10 illustrate the detailed timing for an interrupt
response. After the application of RESET, the CPU automatically enters
interrupt Mode 0.
Mode 1
When this mode is selected by the programmer, the CPU responds to an
interrupt by executing a restart to location 0038H. Thus, the response is
identical to that for a non-maskable interrupt except that the call location is
0038H instead of 0066H. The number of cycles required to complete the
restart instruction is two more than normal due to the two added wait states.
Mode 2
This mode is the most powerful interrupt response mode. With a single 8-bit
byte from the user, an indirect call can be made to any memory location.
In this mode, the programmer maintains a table of 16-bit starting addresses
for every interrupt service routine. This table may be located anywhere in
memory. When an interrupt is accepted, a 16-bit pointer must be formed to
obtain the desired interrupt service routine starting address from the table.
The upper eight bits of this pointer is formed from the contents of the I
register. The
register must be loaded with the applicable value by the
I
programmer, such as
,
. A CPU reset clears the
register so that it is
LD I
A
I
initialized to zero. The lower eight bits of the pointer must be supplied by
the interrupting device. Only seven bits are required from the interrupting
device because the least-significant bit must be a zero. This is required
UM008005-0205
Overview