Z84C2008PEG Zilog, Z84C2008PEG Datasheet - Page 51

• Manufacturer Part Number: Z84C2008PEG
• Description: IC 8MHZ Z80 CMOS PIO 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C2008PEG

• Processor Type: Z80
• Features: Low Power CMOS
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z84C2xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008005-0205
Interfacing Dynamic Memories
CLK
MREQ
Figure 20. Adding One Wait State to Any Memory Cycle
Each individual dynamic RAM has it’s own specifications that require
minor modifications to the examples given here. ZiLOG Application Notes
are available describing how the Z80 CPU is interfaced with most popular
dynamic RAM.
Figure 21 illustrates the logic necessary to interface 8 Kbytes of dynamic
RAM using 18-pin 4K dynamic memories. This logic assumes that the
RAMs are the only memory in the system so that A12 is used to select
between the two pages of memory. During refresh time, all memories in the
system must be read. The CPU provides the correct refresh address on lines
A0 through A6. When adding more memory to the system, it is necessary
to replace only the two gates that operate on A12 with a decoder that oper-
ates on all required address bits. Address buffers and data bus buffers are
generally required for larger systems.
D
C
7474
+5V
S
R
+5V
Q
Q
D
C
7474
+5V
S
R
+5V
Q
Q
Hardware and Software Implementation Examples
7400
WAIT
MREQ
CLK
WAIT
User’s Manual
T
1
Z80 CPU
T
2
T
W
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