MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 73

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Instruction Set Summary
3-2
If <condition>
then <operations>
else <operations>
<operand>tested
sign-extended
<operand>
Dx, Dy
Rx, Ry
Ax, Ay
Dr, Dq
TRAP
STOP
Dh, Dl
<op>
MRn
An
Dc
Dn
Du
Rn
Xn
V
+
~
–
10
Arithmetic addition or postincrement indicator.
Arithmetic subtraction or predecrement indicator.
Arithmetic multiplication.
Arithmetic division or conjunction symbol.
Invert; operand is logically complemented.
Logical AND
Logical OR
Logical exclusive OR
Source operand is moved to destination operand.
Two operands are exchanged.
Any double-operand operation.
Operand is compared to zero and the condition codes are set appropriately.
All bits of the upper portion are made equal to the high-order bit of the lower portion.
Equivalent to Format Offset Word
Enter the stopped state, waiting for interrupts.
The operand is BCD; operations are performed in decimal.
Test the condition. If true, the operations after “then”are performed. If the condition is false and the
optional “else”clause is present, the operations after “else”are performed. If the condition is false
and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description
as an example.
Any Address Register n (example: A3 is address register 3)
Source and destination address registers, respectively.
Data register D7–D0, used during compare.
Data register’s high- or low-order 32 bits of product.
Any Data Register n (example: D5 is data register 5)
Data register’s remainder or quotient of divide.
Data register D7–D0, used during update.
Source and destination data registers, respectively.
Any Memory Register n.
Any Address or Data Register
Any source and destination registers, respectively.
Index Register
(SSP); SSP – 2
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Table 3-1. Notational Conventions
Single- And Double Operand Operations
SSP; (Vector)
Register Specifications
Other Operations
(SSP); SSP – 2
PC
SSP; PC
(SSP); SSP – 4
MOTOROLA
SSP; SR