MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 83

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Instruction Set Summary
Letters cc in the integer instruction mnemonics Bcc, DBcc, and Scc specify testing one of the following conditions:
*Not applicable to the Bcc instructions.
3.1.9 System Control Instructions
Privileged and trapping instructions as well as instructions that use or modify the CCR
provide system control operations. FSAVE and FRESTORE save and restore the nonuser
visible portion of the FPU during context switches in a virtual memory or multitasking
system. The conditional trap instructions, which use the same conditional tests as their
corresponding program control instructions, allow an optional 16- or 32-bit immediate
operand to be included as part of the instruction for passing parameters to the operating
system. These instructions cause the processor to flush the instruction pipe. Table 3-10
summarizes these instructions. See 3.2 Integer Unit Condition Code Computation for more
details on condition codes.
3-12
DBcc, FDBcc
Instruction
Bcc, FBcc
Scc, FScc
FNOP
FTST
CC—Carry clear
LS—Lower or same
CS—Carry set
LT—Less than
EQ—Equal
MI—Minus
F—Never true*
NE—Not equal
NOP
BRA
BSR
RTD
RTR
JMP
RTS
TST
JSR
Operand Syntax
Dn,<label>
#<data>
<label>
<label>
<label>
<ea>
<ea>
<ea>
<ea>
<ea>
none
none
none
none
FPn
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Table 3-9. Program Control Operation Format
GE—Greater than or equal
PL—Plus
GT—Greater than
T—Always true*
HI—Higher
VC—Overflow clear
LE—Less than or equal
VS—Overflow set
Integer and Floating-Point Conditional
B, W, L, S, D, X, P
Operand Size
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
none
none
none
none
none
none
16
16
X
8
Unconditional
Test Operand
Returns
If Condition True, Then PC + d
If Condition False, Then Dn – 1
If Dn
If Condition True, Then 1's
Else 0's
PC + d
SP – 4
Destination
SP – 4
PC + 2
PC + 4
(SP)
(SP)
(SP)
Set Integer Condition Codes
Set Floating-Point Condition Codes
n
PC; SP + 4 + d
CCR; SP + 2
PC; SP + 4
–1, Then PC + d
SP; PC
SP; PC
PC (Integer Pipeline Synchronized)
PC (FPU Pipeline Synchronized)
Destination
PC
PC
(SP); PC + d
(SP); Destination
SP
n
Operation
SP; (SP)
n
SP
PC
Destination;
n
n
Dn
PC
PC; SP + 4
PC
PC
MOTOROLA
SP