MPC5200CBV400 Freescale Semiconductor, MPC5200CBV400 Datasheet - Page 25

• Manufacturer Part Number: MPC5200CBV400
• Description: IC MPU 32BIT 400MHZ PPC 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CBV400

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• No. Of Pwm Channels: 8
• Digital Ic Case Style: BGA
• Rohs Compliant: No
• Family Name: MPC52xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

3.3.5.4
3.3.6
The PCI interface on the MPC5200 is designed to PCI Version 2.2 and supports 33-MHz and 66-MHz PCI
operations. See the PCI Local Bus Specification [4]; the component section specifies the electrical and
timing parameters for PCI components with the intent that components connect directly together whether
on the planar or an expansion board, without any external buffers or other “glue logic.” Parameters apply
at the package pins, not at expansion board edge connectors.
The MPC5200 is always the source of the PCI CLK. The clock waveform must be delivered to each
33-MHz or 66-MHz PCI component in the system.
measurement points for 3.3 V signaling environments.
Freescale Semiconductor
MDQS (Data Strobe)
t
mem_clk
t
Sym
DQSS
NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Control Signals
PCI
MDQ (Data)
Memory Interface Timing-DDR SDRAM Write Command
MEM_CLK
MEM_CLK
MEM_CLK period
Delay from write command to first
rising edge of MDQS
Description
Write
t
dqss
Table 21. DDR SDRAM Memory Write Timing
Figure 9. DDR SDRAM Memory Write Timing
MPC5200 Data Sheet, Rev. 4
Write
Figure 10
Min
7.5
—
Table 22
Write
shows the clock waveform and required
summarizes the clock specifications.
Electrical and Thermal Characteristics
t
mem_clk
Max
Write
—
+0.4
Units
ns
ns
SpecID
A5.20
A5.21
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