MPC5200CBV400 Freescale Semiconductor, MPC5200CBV400 Datasheet - Page 75

• Manufacturer Part Number: MPC5200CBV400
• Description: IC MPU 32BIT 400MHZ PPC 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CBV400

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• No. Of Pwm Channels: 8
• Digital Ic Case Style: BGA
• Rohs Compliant: No
• Family Name: MPC52xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

5.4.1.2
The wiring of the JTAG_TRST depends on the existence of a board-related debug interface (see
below).
Normally this interface is implemented, using a COP (common on-chip processor) connector. The COP
allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to
access and control the internal operations of the MPC5200.
5.4.2
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a
COP connector.
5.4.2.1
The MPC5200 functional pin interface and internal logic provides access to the embedded G2_LE
processor core through the Freescale (formerly Motorola) standard COP/BDM interface.
the COP/BDM interface signals. The pin order shown reflects only the COP/BDM connector order.
Freescale Semiconductor
required assertion of JTAG_TRST
JTAG_TRST
PORRESET
G2_LE COP/BDM Interface
Connecting JTAG_TRST
Boards interfacing the JTAG port via a COP connector
Pin #
BDM
16
15
14
13
12
11
10
9
TEST_SEL_0
JTAG_TMS
MPC5200
HRESET
SRESET
I/O Pin
—
—
—
—
Figure 54. PORRESET vs. JTAG_TRST
Table 53. COP/BDM Interface Signals
Connector
MPC5200 Data Sheet, Rev. 4
ckstp_out
hreset
sreset
BDM
GND
GND
KEY
N/C
tms
PullUp/Down
100k Pull-Up
Internal
—
—
—
—
—
optional assertion of JTAG_TRST
PullUp/Down
10k Pull-Up
10k Pull-Up
10k Pull-Up
External
—
—
—
—
—
System Design Information
I/O
—
—
—
—
O
O
O
I
Table 53
1
Table 53
gives
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