MC68020EH16E Freescale Semiconductor, MC68020EH16E Datasheet - Page 102

• Manufacturer Part Number: MC68020EH16E
• Description: IC MPU 32BIT 33MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020EH16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Table 5-8 lists various combinations of control signal sequences and the resulting bus
cycle terminations. To ensure predictable operation, BERR and HALT should be negated
according to parameters #28 and #57 in Section 10 Electrical Characteristics.
DSACK1/DSACK0, BERR, and HALT may be negated after AS. If DSACK1/DSACK0 or
BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated
prematurely.
Example A:
Example B:
5.5.1 Bus Errors
The BERR signal can be used to abort the bus cycle and the instruction being executed.
BERR takes precedence over DSACK1/DSACK0, provided it meets the timing constraints
described in Section 10 Electrical Characteristics. If BERR does not meet these
constraints, it may cause unpredictable operation of the MC68020/EC020. If BERR
remains asserted into the next bus cycle, it may cause incorrect operation of that cycle.
When BERR is issued to terminate a bus cycle, the MC68020/EC020 may enter exception
processing immediately following the bus cycle, or it may defer processing the exception.
The instruction prefetch mechanism requests instruction words from the bus controller and
the instruction cache before it is ready to execute them. If a bus error occurs on an
instruction fetch, the processor does not take the exception until it attempts to use that
instruction word. Should an intervening instruction cause a branch or should a task switch
occur, the bus error exception does not occur.
MOTOROLA
A system uses a watchdog timer to terminate accesses to an unpopulated address
space. The timer asserts BERR after timeout (case 3).
A system uses error detection and correction on RAM contents. The designer may:
1. Delay DSACK1/DSACK0 assertion until data is verified and assert BERR and
2. Delay DSACK1/DSACK0 assertion until data is verified and assert BERR with or
3. Assert DSACK1/DSACK0 prior to data verification. If data is invalid, BERR is
4. Assert DSACK1/DSACK0 prior to data verification; if data is invalid, assert BERR
HALT simultaneously to indicate to the processor to automatically retry the error
cycle (case 5) or, if data is valid, assert DSACK1/DSACK0 (case 1).
without DSACK1/DSACK0 if data is in error (case 3). This configuration initiates
exception processing for software handling of the condition.
asserted on the next clock cycle (case 4). This configuration initiates exception
processing for software handling of the condition.
and HALT on the next clock cycle (case 6). The memory controller can then
correct the RAM prior to or during the automatic retry.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
M68020 USER’S MANUAL
5- 55