MC68020EH16E Freescale Semiconductor, MC68020EH16E Datasheet - Page 170

• Manufacturer Part Number: MC68020EH16E
• Description: IC MPU 32BIT 33MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020EH16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The second word of the cpTRAPcc instruction format contains the coprocessor condition
selector in bits 5–0 and should contain zeros in bits 15–6 (these bits are reserved by
Motorola) to maintain compatibility with future M68000 products. This word is written to the
condition CIR to initiate execution of the cpTRAPcc instruction.
If the coprocessor requires additional information to evaluate a condition, the instruction
can include this information in extension words. These extension words follow the word
containing the coprocessor condition selector field in the cpTRAPcc instruction format.
The operand words of the cpTRAPcc F-line operation word follow the coprocessor-defined
extension words. These operand words are not explicitly used by the MC68020/EC020,
but can be used to contain information referenced by the cpTRAPcc exception handling
routines. The valid encodings for bits 2–0 of the F-line operation word and the
corresponding numbers of operand words are listed in Table 7-1. Other encodings of
these bits are invalid for the cpTRAPcc instruction.
7.2.2.4.2 Protocol. Figure 7-8 shows the protocol for the cpTRAPcc instructions. The
MC68020/EC020 transfers the condition selector to the coprocessor by writing the word
following the operation word to the condition CIR. The main processor then reads the
response CIR to determine its next action. The coprocessor can return a response
primitive to request any services necessary to evaluate the condition. If the coprocessor
returns the true condition indicator, the main processor initiates exception processing for
the cpTRAPcc exception (refer to 7.5.2.4 cpTRAPcc Instruction Traps). If the
coprocessor returns the false condition indicator, the main processor executes the next
instruction in the instruction stream.
7.2.3 Coprocessor Context Save and Restore Instructions
The coprocessor context save and context restore instruction categories in the M68000
coprocessor interface support multitasking programming environments. In a multitasking
environment, the context of a coprocessor may need to be changed asynchronously with
respect to the operation of that coprocessor. That is, the coprocessor may be interrupted
at any point in the execution of an instruction in the general or conditional category to
begin context change operations.
In contrast to the general and conditional instruction categories, the context save and
context restore instruction categories do not use the coprocessor response primitives. A
set of format codes defined by the M68000 coprocessor interface communicates status
MOTOROLA
Opmode
Table 7-1. cpTRAPcc Opmode Encodings
Freescale Semiconductor, Inc.
010
011
100
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M68020 USER’S MANUAL
Operand Words in Instruction Format
One
Two
Zero
7- 17