MC68EC040RC25A Freescale Semiconductor, MC68EC040RC25A Datasheet - Page 121

• Manufacturer Part Number: MC68EC040RC25A
• Description: IC MPU 32BIT 25MHZ 179-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

6.1 OVERVIEW
Figure 6-1 illustrates a block diagram of the M68040 implementation of IEEE standard
1149.1A. The test logic includes a 16-state dedicated TAP controller. These 16 controller
states are defined in detail in the IEEE standard 1149.1A, but only 8 are included in this
section.
The TAP controller provides access to five dedicated signal pins:
The test logic also includes an instruction shift register and two test data registers, a
boundary scan register and a bypass register. The boundary scan register links all device
signal pins into the instruction shift register.
6-2
TCK—A test clock input that synchronizes the test logic.
TMS—A test mode select input with an internal pullup resistor sampled on the rising
TDI—A test data input with an internal pullup resistor sampled on the rising edge of
TDO—A three-state test data output actively driven only in the shift-IR and shift-DR
TRST —An active-low asynchronous reset with an internal pullup resistor that forces
TCK.
edge of TCK to sequence the TAP controller.
controller states that changes on the falling edge of TCK.
the TAP controller into the test-logic-reset state.
TRST
TMS
TCK
TDI
Figure 6-1. M68040 Test Logic Block Diagram
Freescale Semiconductor, Inc.
Test-Logic-Reset
Capture-IR
Update-IR
Shift-IR
For More Information On This Product,
183
184-BIT BOUNDARY SCAN REGISTER
BYPASS
2
M68040 USER’S MANUAL
3-BIT INSTRUCTION SHIFT REGISTER
Go to: www.freescale.com
TEST DATA REGISTERS
LATCHED DECODER
Run-Test/Idle
Capture-DR
Update-DR
Shift-DR
0
0
TDO
MOTOROLA