LE80538VE0041M Intel, LE80538VE0041M Datasheet - Page 15

• Manufacturer Part Number: LE80538VE0041M
• Description: IC PROC CELERON M 1.06GHZ 479BGA
• Manufacturer: Intel

Specifications of LE80538VE0041M

• Processor Type: Celeron M
• Features: 533MHZ Bus, 1M L2 Cache
• Speed: 1.06GHz
• Voltage: 0.94V
• Mounting Type: Surface Mount
• Package / Case: 479-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 883549

3
3.1
3.2
3.3
Intel
®
Celeron
®
M Processor Datasheet
Electrical Specifications
FSB and GTLREF
The Intel Celeron M processor FSB uses Advanced Gunning Transceiver Logic (AGTL+)
signalling technology, a variant of GTL+ signalling technology with low power enhancements.
This signalling technology provides improved noise margins and reduced ringing through low-
voltage swings and controlled edge rates. The termination voltage level for the Intel Celeron M
processor AGTL+ signals is VCCP = 1.05 V (nominal). Due to speed improvements to data and
address bus, signal integrity and platform design methods have become more critical than with
previous processor families. Design guidelines for the Intel Celeron M processor FSB will be
detailed in the platform design guides.
The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine
if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board.
Termination resistors are provided on the processor silicon and are terminated to its I/O voltage
(VCCP). Intel’s 855PM, 855GM, and 852GM chipsets will also provide on-die termination, thus
eliminating the need to terminate the bus on the system board for most AGTL+ signals.
Refer to the platform design guides for board level termination resistor requirements.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
FSB, including trace lengths, is highly recommended when designing a system.
Power and Ground Pins
For clean on-chip power distribution, the Intel Celeron M processor will have a large number of
V
all V
is recommended to reduce I
The processor V
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low- and full-power states. This may cause
voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Care must be taken in the board design to ensure that the voltage provided to the processor remains
within the specifications listed in
reduced lifetime of the component. For further information and design guidelines, refer to the
platform design guides.
CC
(power) and V
SS
pins must be connected to system ground planes. Use of multiple power and ground planes
CC
SS
pins must be supplied the voltage determined by the VID (Voltage ID) pins.
(ground) inputs. All power pins must be connected to V
x
R drop. Please refer to the platform design guides for more details.
Table
5. Failure to do so can result in timing violations or
Electrical Specifications
CC
power planes while
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