LE80538VE0041M Intel, LE80538VE0041M Datasheet - Page 61

• Manufacturer Part Number: LE80538VE0041M
• Description: IC PROC CELERON M 1.06GHZ 479BGA
• Manufacturer: Intel

Specifications of LE80538VE0041M

• Processor Type: Celeron M
• Features: 533MHZ Bus, 1M L2 Cache
• Speed: 1.06GHz
• Voltage: 0.94V
• Mounting Type: Surface Mount
• Package / Case: 479-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 883549

Intel
®
Table 25. Signal Description (Sheet 6 of 7)
Celeron
®
M Processor Datasheet
SLP#
SMI#
STPCLK#
TCK
TDI
TDO
TEST1,
TEST2,
TEST3
THERMDA
THERMDC
THERMTRIP# Output
TMS
Name
Input
Input
Input
Input
Input
Output
Input
Other
Other
Input
Type
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing internal clock
signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor
will recognize only assertion of the RESET# signal, deassertion of SLP#, and
removal of the BCLK input while in Sleep state. If SLP# is deasserted, the
processor exits Sleep state and returns to Stop-Grant state, restarting its internal
clock signals to the bus and processor core units. If DPSLP# is asserted while in
the Sleep state, the processor will exit the Sleep state and transition to the Deep
Sleep state.
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, the processor saves the
current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution
from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tristate
its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the FSB and APIC units. The processor continues to snoop bus
transactions and service interrupts while in Stop-Grant state. When STPCLK# is
deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#
is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus (also
known as the Test Access Port).
Please refer to the ITP700 Debug Port Design Guide and the platform design
guides for termination requirements and implementation details.
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
Please refer to the ITP700 Debug Port Design Guide and the platform design
guides for termination requirements and implementation details.
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG* specification support.
Please refer to the ITP700 Debug Port Design Guide and the platform design
guides for termination requirements and implementation details.
TEST1, TEST2, and TEST3 must be left unconnected but should have a stuffing
option connection to V
to the platform design guides for more details.
Thermal Diode Anode.
Thermal Diode Cathode.
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature
to ensure that there are no false trips. The processor will stop all execution when
the junction temperature exceeds approximately 125°C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
For termination requirements please refer to the platform design guides.
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
Please refer to the ITP700 Debug Port Design Guide and the platform design
guides for termination requirements and implementation details.
SS
separately using 1-k, pull-down resistors. Please refer
Description
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