MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 46

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 2-5 describes the channel mode register’s fields for HDLC operation. Boldfaced
parameters must be initialized by the user.
0
1
2
3
4–6
7
8
9
Field
MODE
—
IDLM
ENT
—
POL
CRC
—
Name
Mode—Each channel has a programmable option whether to use transparent mode or HDLC
mode.
0 Transparent mode
1 HDLC mode
0
Idle mode.
0 Idle mode is disabled. No idle patterns are transmitted between frames. After transmitting the
1 Idle mode enabled. At least one idle pattern is transmitted between adjacent frames. If
If in IDLE mode and NOF = 1, the following sequence is transmitted:
......init value, FF, FF, flag, flag, data,......
The init value before the idle will be 1’s, in this case it is assumed the transmitter was
uninitialized. An uninitialized SCC transmits 1s in every position.
Enable transmit.
0 Disable transmitter. If this bit is cleared and the channel’s transmitter is routed to a certain
1 The transmit portion of the channel is enabled and data is sent according to protocol and to
Reserved
Enable polling. This bit enables the transmitter to poll the transmit buffer descriptors.
0 The CPM does not check the ready bit (R) in the transmit buffer descriptor.
1 The CPM checks the ready bit (R) in the transmit buffer descriptor.
The user can use this bit to prevent unnecessary external bus cycles when checking the ready bit
(R) in the buffer descriptor. This bit should always be set by the software at the beginning of a
transmit sequence of one or more frames. This bit is cleared (0) by the RISC processor when no
more buffers are ready in the transmit queue when it finds a buffer descriptor with the R bit
cleared (0), i. e., at the end of a frame or at the end of a multiframe transmission. In order to
prevent deadlock the software should always prepare the new BD, or multiple BDs, and set (1)
the ready bit in the BD, before setting (1) the POL bit.
Note that as this bit is automatically cleared by the CPM; the user should not attempt to clear this
bit in software.
This bit selects the type of CRC when using the HDLC channel mode.
0 16-bit CCITT-CRC is selected for this channel.
1 32-bit CCITT-CRC is selected.
0
NOF + 1 flags, the transmitter starts the data of the frame. If between frames and the frame
buffer is not ready, the transmitter sends flags until it can start transmitting the data. The NOF
shall be greater or equal to the PAD setting; see Section 5.2, “Transmit Buffer Descriptor.” If
NOF = 0, this is identical to flag sharing in HDLC mode. For a high CPM load or with long bus
latencies, the QMC protocol may insert additional flags.
between frames and the frame buffer is not ready, the transmitter sends idle characters. When
data is ready, the NOF + 1 flags are sent followed by the data frame.
time slot (within TSATTx, see Figure 2-3) the transmitter sends 1’s on this time slot.
other control settings.
Note that there is no ENR bit in the QMC protocol. To enable the receiver, the ZDSTATE and
RSTATE parameters shall be set to their initial values.
Freescale Semiconductor, Inc.
Table 2-5. CHAMR Field Descriptions (HDLC)
For More Information On This Product,
Go to: www.freescale.com
QMC Supplement
Description