MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 72

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

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Field
Table 5-1. Receive Buffer Descriptor (RxBD) Field Descriptions (Continued)
Name
—
W
I
L
F
CM
—
UB
—
LG
—
Wrap (final buffer descriptor in table)
0 This is not the last buffer descriptor in the RxBD table.
1 This is the last buffer descriptor in the RxBD table. After this buffer is used, the CPM receives
Interrupt
0 The RXB bit will not be set after this buffer has been used, but RXF operation remains
1 The RXB bit (and/or the RXF bit in HDLC mode) of the interrupt table entry will be set when
Last-in-frame (HDLC mode only)—The HDLC controller sets L when this buffer is the last in a
frame. This implies the receipt of a closing flag or reception of an error, in which case one or more
of the CD, OV, AB, and LG bits are set. The HDLC controller writes the number of frame octets to
the data length field.
0 This buffer is not the last in a frame.
1 This buffer is the last in a frame.
First-in-frame—The controller sets this bit when this buffer is the first in a frame.
0 The buffer is not the first in a frame.
1 The buffer is the first in a frame.
Continuous Mode
0 Normal operation.
1 The empty bit is not cleared by the CPM after this buffer descriptor is closed, allowing the
—
User bit—The CPM never touches, sets, or clears this user-defined bit. The user determines how
this bit is used. For example, it can be used to signal between higher level protocols whether a
buffer has been processed by the CPU.
—
Rx frame length violation (HDLC mode only)—A frame length greater than the maximum value
was received in this channel. Only the maximum-allowed number of bytes, MFLR rounded to the
nearest higher longword alignment, are written to the data buffer. This event is recognized as
soon as the MFLR value is exceeded when data is long-word-aligned. When data is not long-
word-aligned, this interrupt occurs when the SDMA writes 32 bits to memory. The worst-case
latency from MFLR violation until detected is 3-byte timings for this channel. When MFLR
violation is detected, the receiver is still receiving even though the data is discarded. The buffer is
closed when a flag is detected, and this is considered to be the closing flag for this buffer. At this
point, LG = 1 and an interrupt may be generated. The length field for this buffer includes
everything between the opening flag and this last identified flag.
incoming data into the first buffer descriptor in the table (the buffer descriptor pointed to by
RBASE). The number of RxBDs in this table is programmable and is determined only by the
wrap bit and by the space constraints of the dual-ported RAM.
unaffected.
this buffer has been used by the HDLC controller. These two bits may cause interrupts (if
enabled).
associated data buffer to be overwritten automatically when the CPM next accesses this
buffer descriptor. The empty bit is not cleared if an error occurs during reception. The user
must terminate continuous mode by clearing this bit.
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