MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 50

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

2.4.2 Channel-Specific Transparent Parameters
Table 2-10 describes the channel-specific transparent parameters. Boldfaced parameters
must be initialized by the user.
00
02
04
08
0C
0E
10
14
18
1C
1E
20
Offset
0–1
2
3
4
5–7
Field
—
—
MOT
—
AT[1–3]
TBASE
CHAMR
TSTATE
TBPTR
TUPACK
ZISTATE
RES
INTMSK
BDFlags
RBASE
Name
Name
Table 2-9. RSTATE Field Descriptions for 860MH (HDLC)
Table 2-10. Channel-Specific Transparent Parameters
0
1
Motorola/Intel bit
0 = The bus format is Intel format (little-endian).
1 = The system bus is considered to be organized in Motorola format (big-endian).
0
Address type—This field contains the address type for the transmitter DMA channel for data
buffers in external memory (transmit buffers). Address types are needed by the memory
controller to decode a correct memory cycle and activate the correct handshaking.
Freescale Semiconductor, Inc.
Width
16
16
32
32
16
16
32
32
32
16
16
16
For More Information On This Product,
Tx buffer descriptor base address—Defines the offset of the channel’s transmit BD
table relative to MCBASE, host-initialized. See Figure 2-2.
Channel mode register. See Section 2.4.2.1, “CHAMR—Channel Mode Register
(Transparent Mode).”
Tx internal state —TSTATE defines the internal Tx state.
Host-initialized to 0x3800
Host-initialized to 0x3000
Initialize before enabling the channel. See Section 2.4.2.2, “TSTATE—Tx Internal
State (Transparent Mode).”
Tx internal data pointer—Points to current absolute address of channel.
Tx buffer descriptor pointer (host-initialized to TBASE before enabling the channel
or after a fatal error before reinitializing the channel)—Contains the offset of
current BD relative to MCBASE. See Table 2-1. MCBASE + TBPTR gives the
address for the BD in use.
Tx internal byte count—Number of remaining bytes
(Tx temp) Unpack 4 bytes from 1 long word
Zero-insertion machine state (host-initialized to 0x0000
previous state of the zero-insertion state machine.
Channel’s interrupt mask flags. See Figure 2-9.
Temp
Receive buffer descriptor base offset—Defines the offset of the channel’s 64-Kbyte
receive BD table relative to MCBASE. Host-initialized. See also Figure 2-2.
Go to: www.freescale.com
QMC Supplement
_
_
0000—FC = 8, Motorola mode for MH360.
0000—AT = 0, Motorola mode for 860MH.
Description
Description
_
0100)—Contains the