MPC180LMB Freescale Semiconductor, MPC180LMB Datasheet
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... Freescale Semiconductor, Inc. MPC180LMB Security Processor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product, User’s Manual Go to: www.freescale.com Rev. 1, 3/2002 ...
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... Freescale Semiconductor, Inc. DigitalDNA, PowerQUICC, and PowerQUICC II are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation registered trademark of Philips Semiconductors This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice ...
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... Freescale Semiconductor, Inc. External Bus Interface and Memory Map Data Encryption Standard Execution Unit Message Digest Execution Unit Public Key Execution Unit Random Number Generator Glossary of Terms and Abbreviations PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Overview 1 Signal Descriptions 2 External Bus Interface and Memory Map 3 Data Encryption Standard Execution Unit 4 Arc Four Execution Unit 5 Message Digest Authentication Unit 6 Public Key Execution Unit 7 Random Number Generator 8 GLO Glossary of Terms and Abbreviations PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to: www ...
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... Freescale Semiconductor, Inc. Paragraph Number 1.1 Features ............................................................................................................... 1-1 1.2 System Architecture............................................................................................ 1-2 1.3 Architectural Overview....................................................................................... 1-3 1.3.1 Public Key Execution Unit (PKEU) ............................................................... 1-4 1.3.2 Data Encryption Standard Execution Unit (DEU).......................................... 1-4 1.3.3 Arc Four Execution Unit (AFEU) .................................................................. 1-5 1.3.4 Message Authentication Unit (MAU)............................................................. 1-5 1 ...
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... Message Digest Buffer (MA–ME) ................................................................. 6–5 Public Key Execution Unit 7.1 Operational Registers.......................................................................................... 7–1 7.1.1 PKEU Version Identification Register (PKID) .............................................. 7–1 vi MPC180LMB Security Processor User’s Manual For More Information On This Product, CONTENTS Title Chapter 4 Chapter 5 Arc Four Execution Unit Chapter 6 Chapter 7 Go to: www ...
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... Freescale Semiconductor, Inc. Paragraph Number 7.1.2 Control Register (PKCR)................................................................................ 7–2 7.1.3 Status Register (PKSR)................................................................................... 7–3 7.1.4 Interrupt Mask Register (PKMR) ................................................................... 7–4 7.1.5 EXP(k) Register.............................................................................................. 7–6 7.1.6 Program Counter Register (PC)...................................................................... 7–6 7.1.7 Modsize Register ............................................................................................ 7–7 7.1.8 EXP(k)_SIZE.................................................................................................. 7–7 7.2 Memories ............................................................................................................ 7–7 7.3 ECC Routines ..................................................................................................... 7– ...
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... Overview............................................................................................................. 8–1 8.2 Functional Description........................................................................................ 8–1 8.3 Typical Operation ............................................................................................... 8–1 8.4 Random Number Generator Registers ................................................................ 8–2 8.4.1 Status Register ................................................................................................ 8–2 Glossary of Terms and Abbreviations viii MPC180LMB Security Processor User’s Manual For More Information On This Product, CONTENTS Title Go to: www.freescale.com Page Number ...
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... Freescale Semiconductor, Inc. Figure Number 1-1 Typical MPC8xx System Example............................................................................... 1-2 1-2 Typical MPC8260 System Example............................................................................. 1-3 1-3 MPC180 Block Diagram............................................................................................... 1-3 2-1 MPC180 Pin Diagram................................................................................................... 2-4 3-1 MPC180 Execution Unit Registers...............................................................................3–1 3-2 Command/Status Register (CSTAT) ............................................................................3–6 3-3 ID Register ....................................................................................................................3–8 3-4 IMASK Register ...........................................................................................................3– ...
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... Modular Subtract Register Usage ...............................................................................7–30 7-22 Clear Memory Register Usage....................................................................................7–31 2 7-23 R mod N Register Usage ...........................................................................................7–33 7- mod P Register Usage ......................................................................................7– 8-1 RNG Status Register .....................................................................................................8–2 x MPC180LMB Security Processor User’s Manual For More Information On This Product, ILLUSTRATIONS Title Go to: www.freescale.com Page Number ...
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... Freescale Semiconductor, Inc. Table Number 2-1 Pin Descriptions ............................................................................................................ 2-1 3-1 32-Bit System Address Map .........................................................................................3–2 3-2 EBI Registers ................................................................................................................3–5 3-3 CSTAT Field Descriptions ...........................................................................................3–6 3-4 ID Field Descriptions....................................................................................................3–8 3-5 IMASK Field Descriptions ...........................................................................................3–9 3-6 IBCTL Field Descriptions...........................................................................................3–10 3-7 OBCTL Register Field Descriptions...........................................................................3–10 4-1 Data Encryption Standard Execution Unit (DEU) Registers........................................4– ...
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... N ....................................................................................................................7–32 7- mod P ................................................................................................................7– 7-26 Run Time Formulas ....................................................................................................7–35 8-1 Random Number Generator Registers ..........................................................................8–2 8-2 RNG Status Register Field Descriptions.......................................................................8–2 xii MPC180LMB Security Processor User’s Manual For More Information On This Product, TABLES Title Go to: www.freescale.com Page Number ...
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... Freescale Semiconductor, Inc. Chapter 1 Overview This chapter gives an overview of the MPC180 security processor, including the key features, typical system architecture, and the MPC180 internal architecture. 1.1 Features The MPC180 is a flexible and powerful addition to any networking system currently using Motorola’s MPC8xx or MPC826x family of PowerQUICC™ communication processors. ...
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... MPC860 I/O or Network Interface Figure 1-1. Typical MPC8xx System Example 1-2 MPC180LMB Security Processor User’s Manual For More Information On This Product, EEPROM MPC180 System Bus SDRAM Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. EEPROM 60x Bus SDRAM SDRAM DIMMs Figure 1-2. Typical MPC8260 System Example 1.3 Architectural Overview The MPC180 has a slave interface to the MPC8xx system bus and MPC8260 local bus and maps into the host processor’s memory space. Each encryption algorithm is mapped to a unique address space ...
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... K2, K1) or three key (K1, K2, K3) Triple-DES. THe MPC180 supports two of the modes of operation defined for Triple-DES (see draft ANSI Standard X9.52-1998): • TECB (Triple DES analogue of ECB) 1-4 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. • TCBC (Triple DES analogue of CBC) 1.3.3 Arc Four Execution Unit (AFEU) The AFEU processes an algorithm that is compatible with the RC4 stream cipher from RSA Security, Inc. The RC4 algorithm is byte-oriented; therefore, a byte of plaintext is encrypted with a key to produce a byte of ciphertext. The key is variable length, and the AFEU supports 40-bit to 128-bit key lengths, providing a wide range of security levels ...
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... Third-party support for the MPC180 includes a development system for both the MPC860 and the MPC8260. The WindRiver/EST SBC8260C development system and Zephyr Engineering ZPC860C, both of which include a board support package, are available to accelerate customer design cycles. 1-6 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 2 Signal Descriptions This chapter provides a pinout diagram and signal descriptions for the MPC180 security processor. 2.1 Signal Descriptions Table 2-1 groups pins by functionality. Pin Signal Signal name locations type A[18:29] 62, 64, 66, I Address—address bus from the processor core. These bits are decoded in the 67, 68, 70, MPC180 to produce the individual module select lines to the execution units ...
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... JTAG test data input TDO 44 I JTAG test data output TMS 46 I JTAG test mode select TRST 45 I JTAG test reset 2-2 MPC180LMB Security Processor User’s Manual For More Information On This Product, Description Miscellaneous pins DMA Hardware Handshake pins Clock Test Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Table 2-1. Pin Descriptions (Continued) Pin Signal Signal name locations type IVDD 10, 21, 41, I +1.8 Volts (power pins for core logic) 60, 71, 93 OVDD 5, 15, 25, I +3.3 Volts (Power pins for I/O pads) 35, 43, 65, 81, 88, 97 OVSS 3, 13, 23, ...
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... OVDD 15 D19 16 D11 IVSS 19 D26 20 IVDD 21 D18 22 OVSS 23 D10 24 25 OVDD Figure 2-1. MPC180 Pin Diagram 2-4 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com 75 A27 74 A26 73 A25 72 A24 71 IVDD 70 A23 69 IVSS 68 A22 67 A21 66 A20 65 OVDD ...
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... Freescale Semiconductor, Inc. Chapter 3 External Bus Interface and Memory Map This chapter describes the MPC180 address map, the External Bus Interface (EBI), and EBI registers. 3.1 Execution Unit Registers Each MPC180 execution unit has a dedicated set of registers. The MPC180 has a unified memory map that allows software addressibility to all internal registers ...
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... MPC180LMB Security Processor User’s Manual For More Information On This Product, Processor 32-Bit Address MDEU: 0x000–0x1FF 0x0000_0000 Message buffer(MB0) 0x0000_0004 Message buffer(MB1) 0x0000_0008 Message buffer(MB2) 0x0000_000C Message buffer(MB3) ...
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... Freescale Semiconductor, Inc. Table 3-1. 32-Bit System Address Map (Continued) MPC180 12-Bit Address Processor 32-Bit Address 0x018 0x0000_0060 0x200 0x0000_0800 0x201 0x0000_0804 0x202 0x0000_0808 0x203 0x0000_080C 0x204 0x0000_0810 0x205 0x0000_0814 0x206 0x0000_0818 0x207 0x0000_081C 0x208 0x0000_0820 0x209 0x0000_0824 0x20A 0x0000_0828 0x20B ...
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... MPC180 until the operation completes 3-4 MPC180LMB Security Processor User’s Manual For More Information On This Product, Processor 32-Bit Address RNG: 0x600– ...
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... Freescale Semiconductor, Inc. • Automatic buffer filling and emptying. DREQ1 and DREQ2 stay asserted as long as memory space or data is in the buffers, letting the host load data for the next operation before the current operation finishes • Interrupt routing and masking, which lets the host individually detect interrupts • ...
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... Inactive 1 = Active 18–22 Raw interrupt indicators for individual execution units. These are the unmasked interrupts from the execution units. For bits18–22: 0 interrupt not pending 1 interrupt pending 3-6 MPC180LMB Security Processor User’s Manual For More Information On This Product DR2C DR1C — ...
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... Freescale Semiconductor, Inc. Table 3-3. CSTAT Field Descriptions Bits Name 18 DEU Data Encryption Standard Execution Unit interrupts 19 AFEU Arc Four Execution Unit interrupts 20 MDEU Message Digest Execution Unit interrupts 21 RNG Random Number Generator interrupts 22 PKEU Public key Execution Unit interrupts 23 MPC180 MPC180 IRQ ...
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... All interrupts from the execution units have the same priority. Figure 3-4 shows the bit assignments in the IRQ register for all the MPC180 execution units. All enable (mask) registers operate on the corresponding bits. An interrupt is masked when its corresponding IMASK bit 3-8 MPC180LMB Security Processor User’s Manual For More Information On This Product ...
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... Freescale Semiconductor, Inc. 0 Field Reset R/W 16 Field Reset R/W Addr Table 3-5 describes the IMASK fields. Table 3-5. IMASK Field Descriptions Bits Name 0–26 — Reserved, should be cleared. 27 DEU Data Encryption Standard Execution Unit global interrupt control 0 interrupt unmasked 1 interrupt masked ...
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... Starting address of the output buffer data source. The starting address is the internal offset from which the first word of data to the output buffer is read for a given operation. All subsequent addresses are derived from this address. 3-10 MPC180LMB Security Processor User’s Manual For More Information On This Product ...
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... Freescale Semiconductor, Inc. 3.3.1.5 Input Buffer Count (IBCNT) and Output Buffer Count (OBCNT) Registers IBCNT indicates the number of 32-bit words to be used for an operation. For example, if the PKEU is to operate on 512 bits (16 words), IBCNT should be set to 0x0000_0010, corresponding to sixteen, 32-bit words to be taken from the input buffer and written to the PKEU ...
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... MPC8260 mode) of space are available. Similarly, for the output buffer, DREQx remains asserted as long as at least eight 32-bit words (MPC8260 mode) are in the output buffer to be read. 3-12 MPC180LMB Security Processor User’s Manual For More Information On This Product, NOTE: Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 4 Data Encryption Standard Execution Unit This chapter explains how to program the DEU (Data Encryption Standard Execution Unit) to encrypt or decrypt a message. 4.1 Operational Registers All operational registers within the main control block are 32-bit addressable, however they may contain less than 32 bits. The keys, initialization vector, plaintext and ciphertext are all 64-bit, and each takes two registers. Each has a left (most signifi ...
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... The configuration register contains two bits that are set only during hardware initialization. All unused bits of DCFG are read as 0 values. 0 Field Reset R/W Addr Figure 4-2. DEU Configuration Register (DCFG) 4-2 MPC180LMB Security Processor User’s Manual For More Information On This Product, — 0000_0000_0000_0000 R 0x200 Description — 0000_0000_0000_0000 ...
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... Freescale Semiconductor, Inc. Table 4-3 describes DCFG fields. Table 4-3. DCFG Field Descriptions Bits Name 0–29 — Reserved, should be cleared. 30 RST The DES can be reset by asserting the RESET signal or by setting the Software Reset bit in the Control Register. The software and hardware resets are functionally equivalent. The software reset bit will clear itself one cycle after being set. 0 — ...
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... DATAIN before any are read from DATAOUT, the IRDY bit in the Status register will go low, indicating that any additional blocks written to DATAIN will cause a loss of data due to overwrite. 4-4 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 5 Arc Four Execution Unit This chapter explains how to program the AFEU (Arc Four Execution Unit) to encrypt or decrypt a message. 5.1 Arc Four Execution Unit Registers All operational registers within the main control block are 32-bit addressable. However, they may contain less than 32 bits. ...
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... Asserted whenever the AFEU core is not in an idle state. Memory initialization or permutation and message processing conditions will cause this bit to be set. The Busy bit will be set during context writes/reads. 5-2 MPC180LMB Security Processor User’s Manual For More Information On This Product ...
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... Freescale Semiconductor, Inc. 5.1.2 Control Register Figure 5-2 shows the AFEU Control Register. 0 Field Reset R/W Addr Figure 5-2. Arc Four Execution Unit Control Register Table 5-3 describes the AFEU Control Register fields. Table 5-3. AFEU Control Register Field Descriptions Bit Name 0– ...
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... If the sub-message is less than 32-bits, the unused bits in the Cipher Register will be the same as the corresponding bits written to the Message Register. 5-4 MPC180LMB Security Processor User’s Manual For More Information On This Product, NOTE: 28 — ...
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... Freescale Semiconductor, Inc. 5.1.9 S-box I/J Register The Sbox I/J Register is a 24-bit read/write register where the Sbox I/J pointers are stored. The contents of this register must be read prior to context switching and must be written back to the AFEU before resuming message processing of an interrupted message. This register may be accessed whenever the AFEU is idle. 5.1.10 S-box0 – ...
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... Freescale Semiconductor, Inc. Arc Four Execution Unit Registers 5-6 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 6 Message Digest Execution Unit This chapter explains how to program the MDEU (Message Digest Execution Unit) within the MPC180 to hash a message for authentication. 6.1 Operational Registers All operational registers within the MDEU are 32-bit addressable, however they may contain less than 32 bits ...
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... Field — ENGO OPAD IPAD Reset R/W Addr Figure 6-1. MDEU Control Register (MCR) 6-2 MPC180LMB Security Processor User’s Manual For More Information On This Product, Processor 32-Bit Address 0x0000_004C Message digest (MD) 0x0000_0050 Message digest (ME) 0x0000_0054 Control (MCR) 0x0000_0058 Status (MSR) ...
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... Freescale Semiconductor, Inc. Table 6-2. MCR Field Descriptions Bits Name 0–19 — Reserved, should be cleared. 20 ENGO Enables automatic start of hashing as soon as the MDMB buffers have all been written not necessary to set the GO bit manually. 21 OPAD The assertion of OPAD causes: 1. The value written to the 512 bit Message Buffer to be exclusive-ORed with the outer hash pad value 2 ...
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... Table 6-3. MSR Field Descriptions Bits Name 0–27 – 28 IRQ DONE 6-4 MPC180LMB Security Processor User’s Manual For More Information On This Product, — 0000_0000 R/W — 0000_0000 R/W 0x016 Description Reserved, should be cleared. 0 interrupt not indicated 1 interrupt indicated 0 address error not detected ...
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... Freescale Semiconductor, Inc. 6.1.4 Message Buffer (MB0—MB15) The MDEU hashes a message contained in the 16-word Message Buffer. The message should be processed such that a single-character message would be written to MB0. MB15 should only be programmed if the message block uses at least 481 bits. The Message Buffer is not cleared upon completion of a computation process. Therefore, when programming the fi ...
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... Freescale Semiconductor, Inc. Operational Registers 6-6 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 7 Public Key Execution Unit This chapter explains how to program the PKEU (Public Key Execution Unit) to perform mathematical functions. 7.1 Operational Registers All operational registers within the main control block are 32-bit addressable, however they may contain less than 32 bits. ...
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... When XYZ is zero, the PKEU assists the host in achieving its desired affine coordinate results. This is accomplished by including Z Montgomery residue system the responsibility of the host to find the inverses of Z provide these back to the PKEU to compute the affine coordinates. 0 affine coordinates 1 projective coordinates 7-2 MPC180LMB Security Processor User’s Manual For More Information On This Product ...
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... Freescale Semiconductor, Inc. Table 7-2. PKCR Field Descriptions (Continued) Bits Name For a description mod N enabled mod P enabled RST The RST bit is a software reset signal. When activated, the PKEU will reset immediately. All registers revert to their initial state, and the Program Counter (PC) will jump to 0. Instruction execution will halt, and any pending interrupt will be deactivated. All memories (A, B, and N) will indirectly be reset since this signal causes the “ ...
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... PKMR is set to 1, the corresponding bit in the PKSR will no longer cause the interrupt. The PKMR is a read-write register. Its contents may be read or written by the host processor. 7-4 MPC180LMB Security Processor User’s Manual For More Information On This Product, 10 — E_RDY IRQ ...
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... Freescale Semiconductor, Inc. All unused bits of the PKMR are read as 0 values. Since the PKMR is a 16-bit register, when the host processor reads the PKMR, its contents are copied onto D[15:0], and the upper half driven with 0’s. Figure 7-3 shows the PKEU Interrupt Mask Register and Table 7-4 describes this register’s fi ...
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... The Program Counter is an 11-bit register that contains the address of the next instruction to be executed. This register is a read-write register. During normal routine execution, this register is preloaded with the software routine’s entry address. 7-6 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. 7.1.7 Modsize Register This register sets the maximum size of the modulus (or prime) for RSA and ECC F irreducible polynomial for ECC F digit = 16 bits) for RSA and ECC F to modsize is not checked for validity). Thus, modsize represents the number of 16-bit blocks in the modulus or irreducible ...
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... N0 = prime p (modulus) of the ECC system Run-time EXP( 32-bits of k (provided in 32 bit words throughout the point multiply, msb to lsb); conditions first word provides following routine invocation per ERDY assertion. 7-8 MPC180LMB Security Processor User’s Manual For More Information On This Product, NOTE: NOTE: Point Multiply p ...
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... Freescale Semiconductor, Inc. Table 7-5. ECC F Post-conditions X’ Y’ Z’ undefined (when XYZ = undefined (when XYZ = Unless explicitly noted, all other registers are not guaranteed to be any particular value. Special — conditions Initial Condition 2 R mod ( ( ( prime p ‘1’ - ECC enabled k (run-time) select ‘ ...
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... The following restrictions apply to the point multiply: • The value of the k vector must be greater than one for this function to work properly. • The point multiply operates with a minimum of five digits (Modsize = 4). 7-10 MPC180LMB Security Processor User’s Manual For More Information On This Product ...
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... Freescale Semiconductor, Inc. 7.3.2 ECC F Point Add p This function is extensively utilized by the point multiply routine. However, its value as a stand-alone routine to the host processor is extremely limited result, the information provided on the routine is primarily for testing and debug purposes. Table 7-6. ECC F ...
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... While not explicitly mentioned or necessary, the contents registers A0, A1, and A2 a left undisturbed in anticipation that these will store the generator point (P) during a point multiply. Initial Condition modulus N ‘1’ - ECC enabled Figure 7-6. ECC F 7-12 MPC180LMB Security Processor User’s Manual For More Information On This Product, Point Double p F Point Double p ...
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... Freescale Semiconductor, Inc. 7.3.4 ECC F Modular Add p Modular addition may be performed on any two vectors loaded into A (A0-A3) and B (B0-B3), where both of these vectors are less than the value stored in the modulus register N (N0-N3). The results are stored in the respective B register. For ECC functionality, this function is used by the point add and point double routines but is available to the host interface - typically for higher-level ECC-related functions ...
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... N (if N0 selected) ‘1’ - ECC enabled set (00, 01, 10, 11) set (00, 01, 10, 11) set (00, 01, 10, 11) Figure 7-8. Modular Subtract Register Usage 7-14 MPC180LMB Security Processor User’s Manual For More Information On This Product, Table 7-9. Modular Subtract Modular Subtract Final Condition B3 ? ...
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... Freescale Semiconductor, Inc. 7.3.6 ECC F Montgomery Modular Multiplication mod N) -1 The ( mod N calculation is the core function of the PKEU used to assist the point add and double routines in completing their functions. For ECC purposes, this function will rarely be used directly by the host processor. This function operates with a minimum of fi ...
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... A (if A0 selected) modulus N (if N0 selected) set (00, 01, 10, 11) set (00, 01, 10, 11) set (00, 01, 10, 11) Figure 7-10. Modular Multiplication (with double reduction) Register Usage 7-16 MPC180LMB Security Processor User’s Manual For More Information On This Product, Modular Multiply (with double reduction) Final Condition ...
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... Freescale Semiconductor, Inc. 7.3.8 ECC F m Polynomial-Basis Point Multiply 2 The PKEU performs the elliptic curve point multiply function which is the highest level of ECC abstraction supported by the device the intention that the host processor use the PKEU in such a way as to support ECC schemes defined in IEEE P1363 (and other ECC standards) where the point multiply is the critical and most computationally intensive, but not fi ...
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... The point multiplication is optimized to efficiently produce results for systems that work in the projective coordinate scheme but can accelerate affine schemes as well. The host processor selects the scheme via the CR XYZ-bit. 7-18 MPC180LMB Security Processor User’s Manual For More Information On This Product, Final Condition B3 Z (or Z’ ...
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... Freescale Semiconductor, Inc. For affine coordinate systems (XYZ = 0): The results of the calculation are returned to the A and B storage registers. Note that these values correspond to the projective coordinate values the Montgomery residue system. In order to put the projective coordinates into their affine form, the following equations which define their relationships must be calculated: ...
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... All variables followed with the tick mark (‘) indicate the Montgomery residue system. Initial Condition irred. poly. ‘1’ - ECC enabled ‘1’ Figure 7-12. ECC F 7-20 MPC180LMB Security Processor User’s Manual For More Information On This Product, m Point Add Point Add 2 ...
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... Freescale Semiconductor, Inc. 7.3.10 ECC F m Point Double 2 This function is extensively utilized by the point multiply routine. However, its value as a stand-alone routine to the host processor is extremely limited result, the information provided on the routine is primarily for testing and debug purposes. Table 7-14. ECC F ...
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... Initial Condition E (if B0 selected) D (if A0 selected) irred. poly. (if N0 selected) set (00, 01, 10, 11) set (00, 01, 10, 11) set (00, 01, 10, 11) Figure 7-14 7-22 MPC180LMB Security Processor User’s Manual For More Information On This Product, m Modular Add (Subtract Modular Add (Subtract) 2 Final Condition B3 ? ...
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... Freescale Semiconductor, Inc. 7.3.12 ECC F m Montgomery Modular Multiplication The ( mod N calculation is the core function of the PKEU. This function is used to assist the point add and double routines in completing their functions. For ECC purposes, this function will rarely be used directly by the host processor. This function operates with a minimum of 5 digits (Modsize = 4) ...
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... ECC enabled ‘1’ set (00, 01, 10, 11) set (00, 01, 10, 11) set (00, 01, 10, 11) Figure 7-16 Modular Multiplication (with double reduction) Register Usage 2 7-24 MPC180LMB Security Processor User’s Manual For More Information On This Product Modular Multiply (with double reduction Final Condition B3 ...
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... Freescale Semiconductor, Inc. 7.4 RSA Routines For the RSA-related descriptions which follow generally recommended that all memory block pointers (regAsel, regBsel, etc.) are set to zero. For the modular exponentiation routine, the pointers are actually ignored. For the multiplies, add, subtract, 2 and R functions possible to set these pointers and have the PKEU adhere to these settings ...
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... N (bits 1023:512) modulus N (bits 511:0) ‘0’ - ECC disabled exponent (run-time) ‘0’ - integer-mod-n enabled Figure 7-17. Integer Modular Exponentiation Register Usage 7-26 MPC180LMB Security Processor User’s Manual For More Information On This Product, Integer Modular Exponentiation Final Condition B3 B2 etc. ...
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... Freescale Semiconductor, Inc. 7.4.2 RSA Montgomery Modular Multiplication -1 (( mod N) -1 The ( mod N calculation is the core function of the PKEU used to assist the exponentiation routine in completing its operation though it is also available to the host processor - typically to put messages into the Montgomery format. This function operates with a minimum of fi ...
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... Unless explicitly noted, all other registers are not guaranteed to be any particular value. Special — conditions Initial Condition modulus N( ) ‘0’ - integer-modulo-n enabled Figure 7-19. Modular Multiplication (with double reduction) Register Usage 7-28 MPC180LMB Security Processor User’s Manual For More Information On This Product, Modular Multiply (with double reduction) Final Condition ...
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... Freescale Semiconductor, Inc. 7.4.4 RSA Modular Add Modular addition may be performed on any two vectors loaded into A (A0-A3) and B (B0-B3), where both of these vectors are less than the value stored in the modulus register N (N0-N3). The results are stored in the respective B register. This function is particularly helpful when using the Chinese Remainder Theorem ...
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... The function operates the same regardless of whether or not the operands are in the Montgomery conditions residue system. Initial Condition modulus N( ) ‘0’ - ECC disabled ‘0’ - integer-modulo-n enabled Figure 7-21. Modular Subtract Register Usage 7-30 MPC180LMB Security Processor User’s Manual For More Information On This Product, Modular Subtract Final Condition ...
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... Freescale Semiconductor, Inc. 7.5 Miscellaneous Routines The remaining routines are general in nature and are not specific to any particular cryptographic algorithm. 7.5.1 Clear Memory This routine clears all of the RAM memory locations in the PKEU. This includes the A, B, and N RAMs. All locations are set to zero. All other registers are cleared either via a reset (software or hardware explicitly writing zeros to each register ...
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... N N0-3 = modulus Unless explicitly noted, all other registers are not guaranteed to be any particular value. Special — conditions 7-32 MPC180LMB Security Processor User’s Manual For More Information On This Product, 2 mod N, where mod N only supports integer-modulo-n computations (i.e. 2 Table 7-24. R ...
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... Freescale Semiconductor, Inc. Initial Condition modulus N( ) ‘0’ - integer-modulo-n enabled Figure 7-23. R 7.5 mod P Calculation p N The PKEU has the ability to calculate R the number of digits of the modulus P, and E is the number of digits of the modulus N, and < E. This constant is used in performing Chinese Remainder Theorem calculations given modulus where P and Q are prime numbers ...
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... Unless explicitly noted, all other registers are not guaranteed to be any particular value. Special — conditions Initial Condition modulus P( ) ‘0’ - ECC disabled ‘1’ - RpRn enabled ‘0’ - integer-modulo-n enabled Figure 7-24. R 7-34 MPC180LMB Security Processor User’s Manual For More Information On This Product, Table 7-25 mod mod P p ...
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... Freescale Semiconductor, Inc. 7.6 Embedded Routine Performance The formulas listed in Table 7-26 show the run times for the PKHA embedded routines. Many of these are data dependent, which result in variable length run times. For these cases, the average run-time is noted. Table 7-26. Run Time Formulas ...
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... Freescale Semiconductor, Inc. Embedded Routine Performance 7-36 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 8 Random Number Generator This chapter explains how to program the RNG (Random Number Generator) to create a random number. 8.1 Overview The RNG is a digital integrated circuit capable of generating 32-bit random numbers designed to comply with the FIPS-140 standard for randomness and non-determinism. A linear feedback shift register (LSFR) and cellular automata shift register (CASR) are operated in parallel to generate pseudo-random data ...
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... ORDY bit goes high. 19–30 – Reserved. 31 ON/OFF A value of 1 indicates that the RNG is on and the shift registers are randomizing. 8-2 MPC180LMB Security Processor User’s Manual For More Information On This Product, Processor 32-Bit Address Register 0x0000_1800 Status ...
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... Freescale Semiconductor, Inc. Glossary of Terms and Abbreviations The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. Some of the terms and definitions included in the glossary are reprinted from IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, copyright ©1985 by the Institute of Electrical and Electronics Engineers, Inc ...
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... Triple DES. Encryption operation which permutes 64 bit blocks of plaintext with 64 bit keys three times. Triple DES is exponentially stronger than single DES encryption. Glossary-2 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Diffie-Hellman key exchange. A key exchange protocol allowing the participants to agree on a key over an insecure channel. Digest. Commonly used to refer to the output of a hash function, e.g. message digest refers to the hash of a message. Digital signature. The encryption of a message digest with a private key. ...
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... Key. A string of bits used widely in cryptography, allowing people to encrypt and decrypt data; a key can be used to perform other mathematical operations as well. Given a cipher, a key determines the mapping of the plaintext to the ciphertext. Glossary-4 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. L Latency. The number of clock cycles necessary to execute an instruction and make ready the results of that execution for a subsequent instruction. Least-significant bit (lsb). The bit of least value in an address, register, data element, or instruction encoding. Least-significant byte (LSB). The byte of least value in an address, register, data element, or instruction encoding ...
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... Public key. In public-key cryptography this key is made public to all primarily used for encryption but can be used for verifying signatures. Public-key cryptography. Cryptography based on methods involving a public key and a private key. Glossary-6 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. R RC4 algorithm. Byte oriented, therefore a byte of plaintext is encrypted with a permuted substitution box (S-box) key to produce a byte of ciphertext. The key is variable length and supports in byte increments key lengths from 40 bits to 128 bits, providing a wide range of strengths. RNG. Random Number Generator. A device or silicon block which produces numbers or bits which are non-deterministically related to preceding and following numbers or bits, thoroughly unpredictable ...
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... A transaction may be minimally comprised of an address tenure only. Triple DES. See 3DES. U UPM. Universal Programmable Machine. Complex chip select device found on the PowerQUICC and PowerQUICC II. Glossary-8 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. X XOR. A binary bitwise operator yielding the result one if the two values are different and zero otherwise. XOR is an abbreviation for exclusive- OR. For More Information On This Product to: www.freescale.com Glossary-9 ...
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... Freescale Semiconductor, Inc. Glossary-10 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Numerics D, 2-1 signal description D, 2-1 A, 2-1 signal description A, 2-1 A address map, 3–2 AFEU (Arc Four Execution Unit), 1-5, 5–1 AFEU Control Register, 5–3 AFEU Status Register, 5–2 Arc Four Execution Unit, 5–1 Arc Four Execution Unit (AFEU), 1-5 ...
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... NC, 2-2 O OBCNT,seeOutput Buffer Count, 3–11 OBCTL,seeOutput Buffer Control, 3–9 Output Buffer Control Register, 3–9 Output Buffer Count Register, 3–11 Index-2 MPC180LMB Security Processor User’s Manual For More Information On This Product, INDEX OVDD, 2-3 OVSS, 2-3 P pinout, 2-4 PKEU (Public Key Execution Unit), 1-4 Program Counter Register PKEU, 7– ...
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... Freescale Semiconductor, Inc. DATAOUT, 4–4 DEU Configuration, 4–2 DEU Status, 4–3 ID, 3–7 IMASK, 3–8 Input Buffer Control (IBCTL), 3–9 Input Buffer Count (IBCNT), 3–11 Intialization Vector, 4–4 MDEU, 6–1–6–5 MDEU Control, 6–2 MDEU Message Buffer (MB0–MB15), 6–5 MDEU Message Digest Buffer (MA– ...
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... Freescale Semiconductor, Inc. Index-4 MPC180LMB Security Processor User’s Manual For More Information On This Product, INDEX Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. External Bus Interface and Memory Map Data Encryption Standard Execution Unit Message Digest Execution Unit Public Key Execution Unit Random Number Generator Glossary of Terms and Abbreviations For More Information On This Product, Go to: www.freescale.com Overview Signal Descriptions Arc Four Execution Unit ...
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... Freescale Semiconductor, Inc. Overview 1 Signal Descriptions 2 External Bus Interface and Memory Map 3 Data Encryption Standard Execution Unit 4 Arc Four Execution Unit 5 Message Digest Execution Unit 6 Public Key Execution Unit 7 Random Number Generator 8 Glossary of Terms and Abbreviations GLO For More Information On This Product, ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...