MPC180LMB Freescale Semiconductor, MPC180LMB Datasheet - Page 29

• Manufacturer Part Number: MPC180LMB
• Description: IC SECURITY PROCES 66MHZ 100LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MPC180LMB

• Processor Type: Security Processor
• Speed: 66MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

The complete MPC180 register map, including all execution units, is available to the host.
Although the host can access control registers and input and output buffers while an
instruction is executing, it cannot access the execution unit itself.
3.3.1.2 ID Register
Figure 3-3 shows the ID register. Note that the ID register contains a 32-bit value that
identifies the version of MPC180. Its value at reset is 0x0065_1491and should be read with
the ENDIAN mode set to big endian.
24–27
28–30
Bits
18
19
20
21
22
23
31
Destination
UNMASK
MPC180
AUTO-
MDEU
Name
AFEU
PKEU
RNG
DEU
RST
Data Encryption Standard Execution Unit interrupts
Arc Four Execution Unit interrupts
Message Digest Execution Unit interrupts
Random Number Generator interrupts
Public key Execution Unit interrupts
MPC180 IRQ. This bit, when set, indicates an interrupt is pending in the MPC180.
0 interrupt not pending
1 interrupt pending
Destination bits. Only one execution unit on MPC180 can be active at a time through FIFO
accesses, so the host must program CSTAT to enable the appropriate execution unit. The
host must guarantee that all data related to a specific operation has been processed before
updating CSTAT, otherwise unpredictable results occur in MPC180 because the controller
acts on one execution unit at a time.
1000 DEU
1001 AFEU
1010 MDEU
1011 RNG
1100 PKEU
0xxx no active module
Auto-unmask bit. Enables or disables the auto-unmask function. This function is used to
unmask an interrupt from the currently active execution unit. It is to be used when a
execution unit sends a series of intermediate interrupts the host does not want to see. For
example, if the DEU is enabled and active, many interrupts may be generated for
intermediate results. The host, however, may only be interested in the final interrupt that
occurs when the DEU completes processing all of the data. To begin the operation, the host
masks off the interrupts from the DEU and then writes to the auto-unmask bit. Then, when
the DEU completes processing all the data, the controller unmasks the DEU interrupt and
allows the final DEU interrupt (signaling the completion of processing) to be sent to the host.
The host can then read CSTAT to determine that the DEU generated an interrupt and take
appropriate action.
for bits 28–30:
000 disabled
001 enabled
Software reset. Performs the same function as asserting RESET on MPC180. Setting this
bit resets the MPC180 within two MCLK cycles; the controller clears this bit.
0 —
1 chip reset
Chapter 3. External Bus Interface and Memory Map
Freescale Semiconductor, Inc.
Table 3-3. CSTAT Field Descriptions
For More Information On This Product,
Go to: www.freescale.com
Description
External Bus Interface
3-7