MPC180LMB Freescale Semiconductor, MPC180LMB Datasheet - Page 55

• Manufacturer Part Number: MPC180LMB
• Description: IC SECURITY PROCES 66MHZ 100LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MPC180LMB

• Processor Type: Security Processor
• Speed: 66MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

All unused bits of the PKMR are read as 0 values. Since the PKMR is a 16-bit register,
when the host processor reads the PKMR, its contents are copied onto D[15:0], and the
upper half of D is driven with 0’s.
Figure 7-3 shows the PKEU Interrupt Mask Register and Table 7-4 describes this register’s
fields.
Reset
Field
Addr
Bits
15–5 —
4
3
2
1
0
R/W
Name
E_RDY
—
OB
—
DONE
0
Reserved, should be cleared.
The E_RDY (exponent or k ready) bit indicates that the execution unit is ready to accept the
next 32-bit word of exponent data or point multiplier (k) data in the EXP(k) register. The host
processor may poll the status register to determine if this data needs to be provided or rely on
IRQ (if enabled) to signal when to look at the register to determine what data needs to be
provided. A write to the EXP(k) register will clear this bit as well as the associated IRQ (as long
as no other condition has also cause IRQ’s assertion). Note that there is approximately a two
cycle latency associated with the clearing of IRQ following a write to the EXP(k) register.
Since the EXP(k) register is double-buffered, the host response time, while important, is not
critical to meet maximum performance. At a minimum, the host will have 8 integer multiplies for
RSA or 8 point doubles for ECC to provide new data before adversely impacting the run time.
Refer to the run-time formulae (see Table 7-26) to determine the exact time available for the
target operating frequency.
For those instances where the host does not need to know the status of E_RDY (i.e. lower-level
routines), it is recommended that it mask this bit to prevent it from affecting the IRQ signal.
Reserved, should be cleared.
The OB bit of the Status Register is set to 1 if a read or write operation is to an unknown or
reserved address. The contents of the data bus on an out-of-bounds read is indeterminate.
Reserved, should be cleared.
The DONE bit of the status register is set to 1 when a branch to location 0 occurs. All of the
embedded routines cause the DONE bit to be asserted upon completion. Also, upon reset, the
DONE bit is set. This signifies to the host that the PKEU is ready for normal operation following
the reset. Until that time, the PKEU is busy with its boot procedure. This primarily entails
running the “clear all” routine, clearing all embedded RAM.
Figure 7-3. PKEU Interrupt Mask Register (PKMR)
Freescale Semiconductor, Inc.
Table 7-4. PKMR Field Descriptions
For More Information On This Product,
Chapter 7. Public Key Execution Unit
—
Go to: www.freescale.com
0000_0000
0xB03
R/W
Description
10
E_RDY
11
—
12
Operational Registers
OB
13
—
14
DONE
15
7-5