FW80200M733SL678 Intel, FW80200M733SL678 Datasheet - Page 14

• Manufacturer Part Number: FW80200M733SL678
• Description: IC I/O PROCESSOR 733MHZ 241-BGA
• Manufacturer: Intel

Specifications of FW80200M733SL678

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-BGA
• Other names: 844850

Intel
Package Information
Table 3.
Table 4.
14
®
80200 Processor based on Intel
Power Pins
Signal Pin Description (Sheet 1 of 2)
A[15:0]
ABORT
ADS#/LEN[2]
BE[7:0]#
CLK
CWF/
DBusWidth
(Config. Pin)
D[63:0]
DCB[7:0]
DVALID
FIQ#
HLDA
Name
V
V
Name
V
V
January 2003
CCA
CCP
CC
SS
Count
16
64
Count
1
1
8
1
1
8
1
1
1
17
70
25
1
®
XScale
Hld(Q)
Hld(Q)
Hld(Q)
Rst(X)
Hld(Z)
Slp(X)
Rst(1)
Hld(Z)
Slp(1)
Rst(Z)
Slp(Z)
Rst(Z)
Slp(Z)
Rst(Z)
Slp(Z)
Rst(0)
Hld(1)
Slp(0)
Type
I/O
I/O
O
O
O
O
I
I
I
I
I
Positive supply for the core.
Ground.
Positive supply for the I/O pins.
Positive supply for the analog circuitry (PLL).
1
1
1
™
Datasheet - Commercial and Extended Temperature (80200T)
Microarchitecture
Address Bus: Conveys either the upper or lower half of a 32-bit
address during the issue phase of a bus transaction.
Abort Transaction: When asserted during the data phase of a
transaction, this signal causes the remainder of that transaction to
be aborted.
Address Strobe/Length:
During the first cycle of the issue phase, this signal indicates the
start of a bus request.
During the second cycle of the issue phase, this signal is the MSB
of a value which indicates the length of the transaction.
Byte Enable: Signifies which bytes are valid during a write
transaction. When not in use, this bus is floated (Z).
CLK: Clock input for the core logic.
Critical Word First: When active during a data read transaction,
CWF informs the core of the data wrap order.
DBusWidth: While RESET# is asserted, this pin is sampled by the
Intel
configured as 32-bits or 64-bits. When the pin is sampled as ‘0’
during reset, the 80200 assumes a 64-bit bus. When the pin is ‘1’ at
reset, a 32-bit bus is assumed.
Data Bus: Carries data to/from the processor during a bus
transaction. When not in use, this bus is floated (Z).
Data Check Byte: Carries the optional ECC information associated
with the data on the Data bus. When not in use, this bus is floated
(Z).
Data Valid: Asserted when the Data bus carries valid data.
Fast Interrupt Request: When FIQs are enabled, the processor
responds to a low level on this input by taking the FIQ interrupt
exception.
HLDA: This output is asserted when the 80200 has floated the
shared bus signals in response to HOLD.
®
80200 processor to determine when the data bus is to be
Description
Description