FW80200M733SL678 Intel, FW80200M733SL678 Datasheet - Page 8

• Manufacturer Part Number: FW80200M733SL678
• Description: IC I/O PROCESSOR 733MHZ 241-BGA
• Manufacturer: Intel

Specifications of FW80200M733SL678

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-BGA
• Other names: 844850

Intel
Functional Overview
2.2
2.3
8
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80200 Processor based on Intel
Branch Target Buffer (BTB)
Each entry of the 128-entry BTB contains the address of a branch instruction, the target address
associated with the branch instruction, and a previous history of the branch being taken or not
taken. The history is recorded as one of four states: strongly taken, weakly taken, weakly not-taken,
or strongly not-taken. The BTB can be enabled or disabled via coprocessor 15, register 1.
When the address of the branch instruction hits in the BTB and its history is strongly or weakly
taken, the instruction at the branch target address is fetched; when its history is strongly or weakly
not-taken, the next sequential instruction is fetched. In either case the history is updated.
Data associated with a branch instruction enters the BTB the first time the branch is taken. This
data enters the BTB in a slot with a history of strongly not-taken (overwriting previous data when
present).
Successfully predicted branches avoid any branch-latency penalties in the superpipeline.
Unsuccessfully predicted branches result in a 4-5 cycle branch-latency penalty in the superpipeline.
Instruction Memory Management Unit (IMMU)
For instruction prefetches the IMMU controls logical-to-physical address translation, memory
access permissions, memory domain identifications, and attributes (governing operation of the
instruction cache). The IMMU contains a 32-entry, fully associative Instruction Translation
Look-A-Side Buffer (ITLB) that has a round-robin replacement policy. ITLB entries 0-30 can be
locked.
When an instruction prefetch misses in the ITLB, the IMMU invokes an automatic table-walk
mechanism that fetches an associated descriptor from memory and loads it into the ITLB. The
descriptor contains information for logical-to-physical address translation, memory access
permissions, memory domain identifications, and attributes governing operation of the i-cache.
The IMMU then continues the instruction prefetch by using the address translation just entered into
the ITLB. When an instruction prefetch hits in the ITLB, the IMMU continues the prefetch using
the address translation already resident in the ITLB.
Access permissions for each of up to sixteen memory domains can be programmed. When an
instruction prefetch is attempted to an area of memory in violation of access permissions, then the
attempt is aborted and a prefetch abort is sent to the core for exception processing. The IMMU and
DMMU can be enabled or disabled together.
January 2003
®
XScale
™
Datasheet - Commercial and Extended Temperature (80200T)
Microarchitecture