MPC8321ECZQAFDC Freescale Semiconductor, MPC8321ECZQAFDC Datasheet - Page 16

IC MPU PWRQUICC II 516-PBGA

MPC8321ECZQAFDC

Manufacturer Part Number
MPC8321ECZQAFDC
Description
IC MPU PWRQUICC II 516-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8321ECZQAFDC

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
333MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
516-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8323E-MDS-PB
Maximum Clock Frequency
333 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
16 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
Family Name
MPC83xx
Device Core
PowerQUICC II Pro
Device Core Size
32b
Frequency (max)
333MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1V
Operating Supply Voltage (max)
1.05V
Operating Supply Voltage (min)
0.95V
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
516
Package Type
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8321ECZQAFDC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
DDR1 and DDR2 SDRAM
Figure 4
6.2.2
Table 19
16
At recommended operating conditions with D n _GV
MCK cycle time, (MCK/MCK crossing)
ADDR/CMD output setup with respect to MCK
ADDR/CMD output hold with respect to MCK
MCS output setup with respect to MCK
MCS output hold with respect to MCK
MCK to MDQS Skew
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
MDQS[n]
MDQ[x]
shows the input timing diagram for the DDR controller.
provides the output AC timing specifications for the DDR1 and DDR2 SDRAM interfaces.
MCK[n]
MCK[n]
DDR1 and DDR2 SDRAM Output AC Timing Specifications
Parameter
Table 19. DDR1 and DDR2 SDRAM Output AC Timing Specifications
266 MHz
200 MHz
266 MHz
200 MHz
266 MHz
200 MHz
266 MHz
200 MHz
Figure 4. DDR Input Timing Diagram
DD
of (1.8 or 2.5 V) ± 5%.
t
t
MCK
DISKEW
Symbol
t
t
t
t
t
DDKHMH
DDKHAS
DDKHAX
DDKHCS
DDKHCX
t
MCK
1
D0
–0.6
Min
7.5
2.5
3.5
2.5
3.5
2.5
3.5
2.5
3.5
D1
t
DISKEW
Max
0.6
10
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
Notes
2
3
3
3
3
4

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