MMA8205EG Freescale Semiconductor, MMA8205EG Datasheet - Page 12
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MMA8205EG
Manufacturer Part Number
MMA8205EG
Description
Board Mount Accelerometers X- AXIS 50G SOIC 16
Manufacturer
Freescale Semiconductor
Series
MMA82r
Datasheet
1.MMA8104EGR2.pdf
(47 pages)
Specifications of MMA8205EG
Sensing Axis
X
Acceleration
50 g
Sensitivity
8.02 mV/g
Package / Case
SOIC-16
Axis
X or Y
Acceleration Range
±50g
Voltage - Supply
6.3 V ~ 30 V
Output Type
Digital
Bandwidth
-
Interface
SPI
Mounting Type
Surface Mount
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
3.2.3
Two customer-programmable configuration bytes are assigned.
3.2.4
Configuration Byte 1 contains three defined bit functions, plus five bits that can be programmed by the customer to designate any
coding desired for packaging axis, model, etc.
3.2.5
These bits may be assigned by the customer as desired. They are transmitted by MMA81XXEG/MMA82XXEG/MMA82XXTEG
in response to Request Status, Disable Self-Test Stimulus or Enable Self-Test Stimulus commands, as described in
3.2.6
Configuration Byte 2 contains six bits that can be programmed by the customer to control device configuration, along with parity
and lock bits for DEVCFG1 and DEVCFG2.
3.2.6.1
The bits in configuration bytes 1 and 2 are frozen when the LOCK2 bit is programmed. The LOCK2 bit is not included in the parity
check. Locking does not take effect after this bit is programmed until the device has been subsequently reset.
0 - Customer-programmed data area unlocked.
1 - Programming operations inhibited.
The DDIS bit is not affected by LOCK2 and may be programmed at any time.
3.2.6.2
The PAR2 parity bit is used for detecting changes in configuration bytes 1 and 2 along with registers REG-8 through REG-F
(addresses $06 through $0F, inclusive). A fault condition is indicated if a change to parity-protected register data is detected. The
PAR2 bit follows an “even” parity scheme (number of logical HIGH bits including parity bit is even).
If an internal parity error is detected, the device will respond to Read Acceleration Data commands with zero in the data field, as
described in
A parity fault may result from a bit failure within the OTP or the registers which store an image of the OTP during operation. In
the latter case, power-on reset will clear the fault when the registers are re-loaded. A parity fault associated with the OTP array
is a non-recoverable failure.
The parity status of customer programmed data is not monitored if the LOCK2 bit is not programmed to a logic ‘1’ state.
3.2.6.3
When this bit is programmed to a logic ‘1’ value, ground loss errors will be reported if a ground fault condition is detected.
1 - Ground-loss detection circuitry enabled
0 - Ground-loss detection disabled.
MMA81XXEG
12
Address
Address
$06
$07
Customer Data Lock Bit (LOCK2)
Customer Data Parity Bit (PAR2)
Ground Loss Detection Enable (GLDE)
Location
Location
Configuration Bytes
Device Configuration Byte 1 (DEVCFG1)
Attribute Bits (AT1, AT0)
Device Configuration Byte 2 (DEVCFG2)
Section
DEVCFG1
DEVCFG2
Register
Register
4.5.4. The Status (S) bit will be set in either short word or long word responses to indicate the fault condition.
LOCK2
7
7
Table 3-5 Device Configuration Byte 1
Table 3-6 Device Configuration Byte 2
PAR2
6
6
Customer Defined
GLDE
5
5
DDIS
4
4
Bit Function
Bit Function
AD3
3
3
AD2
2
2
Freescale Semiconductor
ATT1
AD1
1
1
Section
Sensors
ATT0
AD0
0
0
4.