MMA8205EG Freescale Semiconductor, MMA8205EG Datasheet - Page 14

• Manufacturer Part Number: MMA8205EG
• Description: Board Mount Accelerometers X- AXIS 50G SOIC 16
• Manufacturer: Freescale Semiconductor
• Series: MMA82r

Specifications of MMA8205EG

• Sensing Axis: X
• Acceleration: 50 g
• Sensitivity: 8.02 mV/g
• Package / Case: SOIC-16
• Axis: X or Y
• Acceleration Range: ±50g
• Voltage - Supply: 6.3 V ~ 30 V
• Output Type: Digital
• Bandwidth: -
• Interface: SPI
• Mounting Type: Surface Mount
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SECTION 4 PHYSICAL LAYER AND PROTOCOL
MMA81XXEG/MMA82XXEG/MMA82XXTEG family is compliant with the DSI Bus Standard, Version 2.0. MMA81XXEG/
MMA82XXEG/MMA82XXTEG is designed to be compatible with either DSI Version 2 or DSI Version 1.1 compliant bus masters.
4.1
Refer to Section 3 of the DSI Bus Standard for information regarding the physical layer interface.
4.2
Refer to Section 4 of the DSI Bus Standard for information regarding the DSI network data link layer interface. Both standard
and enhanced command structures are supported for short word and long word commands.
4.3
DSI Bus Commands which are recognized by MMA81XXEG and the MMA82XXEG/MMA82XXTEG are summarized in
Table
error is detected, or a reserved or unimplemented command is received, the device will not respond.
Following all messages, MMA81XXEG and the MMA82XXEG/MMA82XXTEG disregards the DSI bus voltage level for approxi-
mately 18.5 μs. Within this time, all supported commands except Initialization and Reverse Initialization are guaranteed to be
executed and the device will be ready for the next message. When the bus voltage falls below the signal high logic level (see
Section
message. Exactly one response is attempted; if a noise spike or corrupted transfer occurs, the response is not retried.
If an Initialization or Reverse Initialization command is executed and the Bus Switch (BS) bit is set, MMA81XXEG, MMA82XXEG
and MMA82XXTEG will disregard the bus voltage level for a nominal period of 180 μs. This interval allows for the bus voltage to
recover following closure of the bus switch, while the hold capacitor of a downstream slave charges.
Legend:
BS: Bus Switch Control (0: open, 1: close)
NV: Nonvolatile memory control (1: program NVM)
PA3 - PA0: Device address assigned during Initialization or Reverse Initialization
RA3 - RA0: Internal user data register address
FA2 - FA0: Format register address
FD3 - FD0: Format register data content
MMA81XXEG
14
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
4-1. Detailed descriptions of each supported command are described in subsequent sections of this document. If a CRC
C2
Binary
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
5) after the 18.5 μs period has elapsed, the device will respond as appropriate to a command sent to it in the previous
DSI NETWORK PHYSICAL LAYER INTERFACE
DSI NETWORK DATA LINK LAYER
DSI BUS COMMANDS
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Hex
$C
$D
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$E
$F
Command
Initialization
Request Status
Read Acceleration Data
Not Implemented
Request ID Information
Not Implemented
Not Implemented
Clear
Not Implemented
Read Write NVM
Format Control
Read Register Data
Disable Self-Test Stimulus
Activate Self-Test Stimulus
Reserved
Reverse Initialization
Description
Table 4-1 DSI Bus Command Summary
Size
SW
SW
N/A
SW
N/A
N/A
SW
N/A
SW
SW
N/A
LW
LW
LW
LW
LW
RA3
R/W
D7
NV
NV
—
—
—
—
—
—
0
RA2
FA2
D6
BS
BS
—
—
—
—
—
—
0
RA1
FA1
D5
B1
B1
—
—
—
—
—
—
0
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
RA0
FA0
D4
B0
B0
—
—
—
—
—
—
0
Data
PA3
RD3
FD3
RA3
PA3
Freescale Semiconductor
D3
—
—
—
—
—
—
RD2
PA2
FD2
RA2
PA2
D2
—
—
—
—
—
—
RD1
PA1
FD1
RA1
PA1
D1
—
—
—
—
—
—
Sensors
RD0
RA0
PA0
FD0
PA0
D0
—
—
—
—
—
—