MMA8205EG Freescale Semiconductor, MMA8205EG Datasheet - Page 26

• Manufacturer Part Number: MMA8205EG
• Description: Board Mount Accelerometers X- AXIS 50G SOIC 16
• Manufacturer: Freescale Semiconductor
• Series: MMA82r

Specifications of MMA8205EG

• Sensing Axis: X
• Acceleration: 50 g
• Sensitivity: 8.02 mV/g
• Package / Case: SOIC-16
• Axis: X or Y
• Acceleration Range: ±50g
• Voltage - Supply: 6.3 V ~ 30 V
• Output Type: Digital
• Bandwidth: -
• Interface: SPI
• Mounting Type: Surface Mount
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.6.4.2
This three-bit field selects one of eight format control registers. Format control registers are described in
There is no response if the Format Control Command is received within a DSI short command structure.
4.6.4.3
The seven 4-bit format control registers defined in the DSI 2.0 Bus Specification are shown in
ues assigned to each register following reset are indicated.
The following restrictions apply to format control register operations, in accordance with the DSI 2.0 Bus Specification:
MMA81XXEG
26
D15
A3
•
•
•
Short Word Data Length (8 to 15)
CRC Polynomial - High Nibble
CRC Polynomial - Low Nibble
Attempting to write a value greater than eight to the CRC Length Register will cause the write to be ignored. The contents
of the register will remain unchanged.
Attempting to write a value less than eight to the Short Word Data Length register will cause the write to be ignored. The
contents of the register will remain unchanged.
The contents of the Format Selection register determine whether standard DSI values or the values contained in the
remaining format control registers will be used. The values contained in the remaining format control registers become
effective when this register is successfully written to ‘1111’. If the register is currently cleared, and one of the data bits FD3
- FD0 is not received as a logic ‘1’, the data in the register will remain all zeroes and the device will continue to use
standard DSI format settings. If the register bits FD3 - FD0 are all set and one of the bits is received as a logic ‘0’ value,
the data in the register will remain ‘1111’ and the values contained in the remaining format control registers will continue
to be used.
D14
A2
Format Control Register Selection (FA2 - FA0)
Format Control Registers
CRC Length (0 to 8)
Seed - High Nibble
Seed - Low Nibble
Format Selection
Reserved
D13
A1
Name
D12
A0
Table 4-17 Long Response Structure - Format Control Command
D11
0
Format Control Register
D10
1
Decimal
Table 4-18 Format Control Registers
D9
1
0
1
2
3
4
5
6
7
D8
0
Data
FA2
R/W
0
0
0
0
1
1
1
1
D7
Address
FA2
D6
FA1
0
0
1
1
0
0
1
1
FA1
D5
FA0
D4
FA0
0
1
0
1
0
1
0
1
FD3
D3
FD3
0
0
1
0
0
1
0
0
Table 4-18
FD2
D2
FD1
FD2
Freescale Semiconductor
D1
Default Value
0
0
0
0
1
0
0
0
Section
below. The default val-
FD0
D0
FD1
0
0
1
0
0
0
0
0
4.6.4.3.
0 to 8 bits
CRC
Sensors
FD0
1
1
0
0
0
0
0
0