MAX9856ETL+ Maxim Integrated Products, MAX9856ETL+ Datasheet - Page 23

• Manufacturer Part Number: MAX9856ETL+
• Description: IC CODEC AUDIO LP 40TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Audio Codecr

Specifications of MAX9856ETL+

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 77 / 91
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 91
• Voltage - Supply, Analog: 1.71 V ~ 3.6 V
• Voltage - Supply, Digital: 1.71 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Interface Type: I2C
• Resolution: 18 bit
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 2.9 mA
• Thd Plus Noise: 82 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 18bit
• Adcs / Dacs Signal To Noise Ratio: 91dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DAC Interface Register Bit Descriptions (continued)
Table 6. Common DACNI and ADCNI Values
Note: Values in bold are exact integers that provide maximum full-scale performance.
MCLK (MHz)
11.2896
12
12.288
13
16.9344
18.432
19.2
24
26
27
REGISTER
DPLLEN
DACNI
PCM
DHF
WS
PSCLK
001
001
001
001
010
010
010
011
011
011
______________________________________________________________________________________
8kHz
116A
1062
1000
1062
AAB
B9C
E90
F20
960
F20
PCM Mode Select. PCM determines the format of the LRCLK_D and LRCLK_A signal:
0—The LRCLK_D and LRCLK_A signals have a 50% duty cycle. Left-channel audio is
transmitted during one state of and right-channel audio during the other state.
1—LRCLK_D and LRCLK_A are pulses that indicate the start of a frame of audio data
consisting of two channels. Following the frame sync pulse, 16 bits of left-channel data is
immediately followed by 16 bits of right-channel data. The DDLY and WS bits are ignored when
PCM = 1.
DAC High-Sample Rate Mode:
0—LRCLK_D is less than 50kHz. 8x FIR interpolation filter used.
1—LRCLK_D is greater than 50kHz. 4x FIR interpolation filter used.
Word Size. This bit controls both the DAC and ADC:
0—16 bits.
1—18 bits.
The DAC interface can accept higher than 18-bit words but the additional least significant bits
are ignored.
DAC PLL Enable:
0 (valid for slave and master mode)—The frequency of LRCLK_D is set by the DACNI divider
bits. In master mode, the MAX9856 generates LRCLK_D using the specified divide ratio. In
slave mode, the MAX9856 expects an LRCLK_D as specified by the divide ratio.
1 (valid for slave mode only)—A digital PLL locks on to any externally supplied LRCLK_D signal
regardless of the MCLK frequency. DHF must set high for sample rates above 50kHz.
DAC LRCLK Divider. When DPLLEN is set low, the frequency of LRCLK_D is determined by
DACNI. See Table 6 for common DACNI values:
DACNI = (65536 x 96 x f
DACNI = (65536 x 48 x f
f
f
LRCLK_D
PCLK
DirectDrive Headphone Amplifiers
16kHz
22D4
20C5
1E3F
20C5
1E3F
1D21
2000
1738
1555
4B0
= Prescaled MCLK internal clock frequency (PCLK).
= LRCLK_D frequency.
Low-Power Audio CODEC with
32kHz
2AAB
45A9
3C7F
2E71
3C7F
3A41
4189
4000
4189
258
LRCLK_D
LRCLK_D
LRCLK
44.1kHz
3ACD
5A51
5A51
6000
5833
535F
4000
535F
5048
1B3
)/f
)/f
PCLK
PCLK
48kHz
5ABE
5ABE
for (DHF = 0).
for (DHF = 1).
687D
624E
45A9
624E
6000
4000
5762
190
FUNCTION
88.2kHz (DAC ONLY)
3ACD
5A51
5A51
6000
5833
535F
4000
535F
5048
1B3
96kHz (DAC ONLY)
5ABE
5ABE
687D
45A9
624E
6000
4000
624E
5762
190
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