MAX9856ETL+ Maxim Integrated Products, MAX9856ETL+ Datasheet - Page 40

• Manufacturer Part Number: MAX9856ETL+
• Description: IC CODEC AUDIO LP 40TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Audio Codecr

Specifications of MAX9856ETL+

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 77 / 91
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 91
• Voltage - Supply, Analog: 1.71 V ~ 3.6 V
• Voltage - Supply, Digital: 1.71 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Interface Type: I2C
• Resolution: 18 bit
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 2.9 mA
• Thd Plus Noise: 82 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 18bit
• Adcs / Dacs Signal To Noise Ratio: 91dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section).
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 9). A START
condition from the master signals the beginning of a
transmission to the MAX9856. The master terminates
transmission, and frees the bus, by issuing a STOP con-
dition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
The MAX9856 recognizes a STOP condition at any
point during data transmission except if the STOP con-
dition occurs in the same high pulse as a START condi-
tion. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Figure 9. START, STOP, and REPEATED START Conditions
40
SCL
SDA
______________________________________________________________________________________
S
START and STOP Conditions
Early STOP Conditions
Sr
Bit Transfer
P
The MAX9856 is preprogrammed with a slave address
of 0x20 or 0010000. The address is defined as the 7
most significant bits (MSBs) followed by the read/write
bit. Setting the read/write bit to 1 configures the
MAX9856 for read mode. Setting the read/write bit to 0
configures the MAX9856 for write mode. The address is
the first byte of information sent to the MAX9856 after
the START condition.
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9856 uses to handshake receipt of each byte of
data when in write mode (see Figure 10). The MAX9856
pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully
received. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master retries communication.
The master pulls down SDA during the 9th clock cycle to
acknowledge receipt of data when in read mode. An
acknowledge is sent by the master after each read byte
to allow data transfer to continue. A not acknowledge is
sent when the master reads the final byte of data from the
MAX9856, followed by a STOP condition.
Figure 10. Acknowledge
SDA
SCL
CONDITION
START
1
2
NOT ACKNOWLEDGE
ACKNOWLEDGE
ACKNOWLEDGMENT
8
CLOCK PULSE FOR
Slave Address
Acknowledge
9