MAX9856ETL+ Maxim Integrated Products, MAX9856ETL+ Datasheet - Page 38

• Manufacturer Part Number: MAX9856ETL+
• Description: IC CODEC AUDIO LP 40TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Audio Codecr

Specifications of MAX9856ETL+

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 77 / 91
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 91
• Voltage - Supply, Analog: 1.71 V ~ 3.6 V
• Voltage - Supply, Digital: 1.71 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Interface Type: I2C
• Resolution: 18 bit
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 2.9 mA
• Thd Plus Noise: 82 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 18bit
• Adcs / Dacs Signal To Noise Ratio: 91dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
Table 14. Headset Detect Control Register
Table 15. Impedance Detection Routine
Headset Detection Register Bit Description
38
t
______________________________________________________________________________________
0
t
0x1B
f
REG
JDETEN
TIME
+ 24ms
-24ms
t
t
BIT
0
EN
f
Disable the headphone amplifiers. Set EN = 111 to enable the detection circuitry.
IRQ set high. Indicates that the detection current has reached its final value and the impedance has been
stored in HSDETL, HSDETR, and JSDET.
Once the impedance of HPL, HPR, and JACKSNS has been read, set EN = 000 to shut down the detection
circuitry.
IRQ set high. Indicates that the detection circuitry is completely shut down and the headphone amplifiers can
be reenabled.
Jack Detection Enable
Sleep Mode—Enables pullups on HPL and JACKSNS to detect jack insertion. LSNS and JKSNS are not
valid unless JDETEN = 1 and SHDN = 0.
Normal Mode—Enables the comparator circuitry on JACKSNS to detect voltage changes. JKMIC is not valid
unless JDETEN = 1 and the microphone circuitry is enabled.
Impedance Detection Enable. Enables the impedance detection circuitry for HPL, HPR, and JACKSNS.
When EN = 000 HSDETL, HSDETR, and JSDET are set to 11. See Table 2, Status Register Bit Description
for details on reading the load impedance.
B7
0
B6
0
000
1xx
x1x
xx1
EN
IMPEDANCE DETECTION ENABLE DESCRIPTION
B5
0
B4
0
Disabled
JACKSNS pin impedance sense enabled
HPR pin impedance sense enabled
HPL pin impedance sense enabled
FUNCTION
EVENT
JDETEN
B3
DESCRIPTION
B2
EN
B1
B0