UDA1355H/N2,518 NXP Semiconductors, UDA1355H/N2,518 Datasheet - Page 35

• Manufacturer Part Number: UDA1355H/N2,518
• Description: IC CODEC STER/SUDIO SPDIF 44QFP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1355H/N2,518

• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 98
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935271552518

NXP Semiconductors
Table 18 L3-bus write data
Table 19 L3-bus read data
11 I
11.1
The bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a Serial Data
Line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to the supply voltage (V
resistor when connected to the output stages of a
microcontroller. For a 400 kHz IC the recommendation for
this type of bus from NXP Semiconductors must be
followed (e.g. up to loads of 200 pF on the bus a pull-up
resistor can be used, between 200 to 400 pF a current
source or switched resistor must be used). Data transfer
can only be initiated when the bus is not busy.
2003 Apr 10
handbook, full pagewidth
BYTE
BYTE
Stereo audio codec with SPDIF interface
1
2
3
4
1
2
3
4
5
6
2
C-BUS DESCRIPTION
Characteristics
address
data transfer
data transfer
data transfer
address
data transfer
address
data transfer
data transfer
data transfer
L3-BUS MODE
L3-BUS MODE
SDA
SCL
device address
register address
data byte 1
data byte 2
device address
register address
device address
register address
data byte 1
data byte 2
DD
) via a pull-up
ACTION
ACTION
Fig.17 Bit transfer on the I
data valid
data line
stable;
35
0 or 1
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
allowed
change
D15
D15
of data
D7
D7
0
0
0
1
1
11.2
One data bit is transferred during each clock pulse (see
Fig.17). The data on the SDA line must remain stable
during the HIGH period of the clock pulse as changes in
the data line at this time will be interpreted as control
signals. The maximum clock frequency is 400 kHz. To be
able to run on this high frequency all the inputs and outputs
connected to this bus must be designed for this high speed
I
FIRST IN TIME
FIRST IN TIME
2
C-bus according the NXP specification.
D14
D14
A6
D6
A6
A6
D6
Bit transfer
1
1
1
2
C-bus.
D13
D13
D5
D5
A0
A5
A0
A5
A0
A5
MBC621
D12
D12
A4
D4
A4
A4
D4
1
1
1
D11
D11
D3
D3
A3
A3
A3
0
0
0
Preliminary specification
D10
D10
D2
A2
D2
A2
A2
0
0
0
UDA1355H
LAST IN TIME
LAST IN TIME
D9
D1
D9
D1
A1
A1
A1
0
0
0
D8
D0
A0
D8
D0
A0
A0
0
0
0